Semiconductor integrated circuit having test circuitry with...

Details Semiconductor integrated circuit having test circuitry with... Semiconductor integrated circuit having test circuitry with...

2005-03-09

2008-10-28

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07444569

ABSTRACT:
The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan thereof having functions to output the status values during the scan test therein. At least, a part of the memory device of the scan includes a first signal-outputting unit outputting a signal during the normal operation therein and a second signal-outputting unit outputting a signal during the scan test operation therein, respectively. Where, it is preferable that the first signal-outputting unit has a larger driving capacity to signal lines therein than the second signal-outputting unit, and that a second signal-outputting unit fixes the output signal level during the normal operation thereof, and that the second signal-outputting unit outputs a status value delayed a predetermined period of the operation clock therein compared with the first signal-outputting unit during the scan test thereof, and so on.

REFERENCES:
patent: 5881067 (1999-03-01), Narayanan et al.
patent: 6114892 (2000-09-01), Jin
patent: 6380780 (2002-04-01), Aitken et al.
patent: 6456113 (2002-09-01), Kanba
patent: 6794898 (2004-09-01), Komaki
patent: 2002-311092 (2002-10-01), None
The special topic 2 of the 2002/03 edition of homepage PR Magazine issued by Mentor Graphic Japan Co., Ltd.: What's DFTJ. URL:http//www.mentor.co.jp/N-V/02-03/TOPIC2.html.

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