Semiconductor integrated circuit having test circuit

Details Semiconductor integrated circuit having test circuit Semiconductor integrated circuit having test circuit

1999-05-03

2003-02-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

06519728

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a test circuit such as a boundary scan test circuit as an easily-testing circuit, and the semiconductor integrated circuit has one or more Large Scale Integration (LSI) formed on a printed wiring substrate, each LSI has the boundary scan circuit for executing a connection test to check the connection state among a plurality of LSI and for performing an internal test such as operation test for an internal circuit in the LSI.
2. Description of the Related Art
FIG. 1
is a diagram showing a mounted state of a semiconductor integrated circuit in which a LSI is mounted on a printed wiring substrate. In
FIG. 1
, the reference number
1
designates the printed wiring substrate, and
2
denotes the LSI mounted on the printed wiring substrate
1
. Although
FIG. 1
shows only the LSI
2
on the printed wiring substrate
1
, in general, a plurality of LSI are mounted on the printed wiring substrate
1
to form a system of the semiconductor integrated circuit.
The reference number
2
a
designates a top surface (non-mounting surface) of the LSI
2
,
2
b
designates a bottom surface (mounting surface) of the LSI
2
, and
2
c
denotes a side face (non-mounting surface) of the LSI
2
. The reference number
3
designates each signal pin, and
3
a
indicates a signal pin through which the LSI
2
inputs a clock signal TCK. The reference number
3
b
designates a signal pin for inputting a test mode signal TMS,
3
c
indicates a signal pin for inputting test data TDI, and
3
d
denotes a signal pin for outputting test data TDO. The reference number
4
designates each solder ball.
A description will be given of the operation of the semiconductor integrated circuit.
FIG. 2
is a circuit diagram showing a configuration of the semiconductor integrated circuit including the printed wiring substrate
1
and a plurality of LSI
2
mounted on the printed wiring substrate
1
.
Ordinary, each LSI
2
is mounted on a substrate such as the printed wiring substrate
1
. Like the configuration shown in
FIG. 2
, when a plurality of LSI
2
are mounted on the printed wiring substrate
1
, the plurality of LIS
2
are connected to each other in order to realize functions to be required for the system of the semiconductor integrated circuit. In this system including the plurality of LIS
2
, each LSI
2
incorporates a boundary scan circuit (IEEE 1149.1) as an easily-testing circuit in order to perform diagnosis of the connection state among the plurality of LIS
2
, to execute diagnosis of the function of a single LSI
2
, and the like. It is so designed that the signal pins
3
a
to
3
d
, namely electrodes, formed on the mounting surface
2
b
of each LSI
2
input control signals for controlling the operation of the boundary scan circuit in the LSI
2
, like signals to be required for the operation of the LSI
2
. Accordingly, in order to execute the diagnosis of the connection state among the plurality of LSI
2
and the function of the single LSI
2
, the signal pins
3
a
to
3
d
must input signals to be used for controlling the operation of the boundary scan circuit. However, as shown in
FIG. 1
, the signal pins
3
a
to
3
d
in the LSI
2
are embedded into the substrate
1
after the LSI
2
has been mounted on the printed wiring substrate
1
. Hence, it becomes impossible to input externally-supplied test control signals directly through the signal pins
3
a
to
3
d
. In the prior art, in order to avoid this drawback, through the TDI terminal
3
c
formed at edges of the printed wiring substrate
1
the test signals are supplied to the boundary scan circuit incorporated in the LSI
2
.
FIG. 3
is a diagram showing test operation of a connection state among the plurality of LSI in the semiconductor integrated circuit. In
FIG. 3
, each of the reference characters LSI-A and LSI-B denotes a LSI.
The test method for the connection state among the plurality of LSI will be explained with reference to FIG.
3
.
In the following case, both the LSI-A and the LSI-B incorporate shift registers called as the boundary scan circuits
41
and
42
, respectively. These shift registers are connected in series from the TDI terminal
3
c
(as an input terminal) to the TDO terminal
3
d
(as an output terminal).
At first, optional test data are set into the boundary scan registers
41
incorporated in the LSI-A by sequentially shifting the test data provided through the TDI terminal
3
c
. After the setting of the test data into the boundary scan registers
41
in the LSI-A, the test data are outputted to the boundary scan registers
42
incorporated in the LSI-B and set therein. After this, the test data are sequentially shifted to the TDO terminal
3
d
in the printed wiring circuit
1
.
Second, the test data obtained from the boundary scan registers
42
in the LSI-B through the TDO terminal
3
d
are compared with the test data that have been set in the boundary scan registers
41
in the LSI-A. When both agree, it can be judged that the connection state between the LSI-A and the LSI-B is correct. When both test data do not agree, it can be judged that there is any fault in the connection state between the LSI-A and the LSI-B.
FIG. 4
is a diagram showing test operation only for the LSI-B in the semiconductor integrated circuit.
A method of the operation test for the LSI will be explained with reference to the FIG.
4
.
In
FIG. 4
, the reference number
53
designates an internal circuit in the LSI-B to be tested. Other components are the same of the components in the semiconductor integrated circuit shown in
FIGS. 2 and 3
. Therefore the same reference numbers are used for the same components.
When the operation test for the LSI-B is executed, at first, test data are sequentially shifted from the TDI terminal
3
c
to the boundary scan registers
52
in the LSI-B through the boundary scan register
51
in the LSI-A. After the set of the test data into the boundary scan register
52
in the LSI-B, the test data are outputted to the internal circuit
53
in the LSI-B. The operation of the internal circuit
53
is then executed.
After the completion of the operation of the internal circuit
53
in the LSI-B, the operation results of the internal circuit
53
are outputted to the boundary scan register
54
. The results of the operation test stored in the boundary scan register
54
are sequentially shifted and outputted to an external device (omitted from
FIG. 4
) through the TDO terminal
3
d.
Finally, the results of the operation test obtained through the TDO terminal
3
d
are compared with desired test data that have been prepared in advance. When both agree, it can be judged that the operation of the internal circuit
53
in the LSI-B is correct.
As shown in
FIG. 3
, because the conventional semiconductor integrated circuit has the configuration described above, the connection state between the LSI-A and the LSI-B can be checked by inputting test data through the TDI terminal
3
c
formed at edges of the printed wiring substrate
1
and for outputting the test data through the TDO terminal
3
d
. However, if there is any defect such as a connection defect, a structure defect in at least one of the TDI terminal
3
c
, the TDO terminal
3
d
, and the printed wiring, the test results obtained through the TDO terminal
3
d
cause an erroneous diagnosis or a mistaken even if the connection state between the LSI-A and the LSI-B has not any defect.
In addition to this conventional drawback, when the plurality of LSI are formed on the printed wiring substrate
1
as shown in
FIG. 4
, it must be required to transfer test data through the LSI-A that is not a target LSI in order to set the test data into the LSI-B as a target LSI to be tested. That is, the test data must be transferred to the target LSI-B through the LSI-A. This configuration causes the drawbacks that the operation time of the diagnosis test is increased and the setting of the test data becomes complicated.
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