Semiconductor integrated circuit for outputting data with a high

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

36518901, 365193, 365194, G11C 700

Patent

active

054885809

ABSTRACT:
A semiconductor integrated memory circuit which extends the time that reliable effective data is output by a data output buffer. The circuit includes a switching device operated by a control signal which is determined according to the states of a row address strobe signal and a column address strobe signal. The switching device is conductive when the column address strobe signal is in an active state, and the switching device is nonconductive when the column address strobe signal is in a precharge state, so that effective data is output by the data output buffer until the column address strobe signal becomes active in the next data read cycle.

REFERENCES:
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patent: 4841488 (1989-06-01), Sanada
patent: 4905195 (1990-02-01), Fukuda et al.
patent: 4970693 (1990-11-01), Nozaki et al.
patent: 5003510 (1991-03-01), Kamisaki
patent: 5155705 (1992-10-01), Goto et al.
patent: 5323355 (1994-06-01), Kato

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