Semiconductor integrated circuit device with scan signal...

Details Semiconductor integrated circuit device with scan signal... Semiconductor integrated circuit device with scan signal...

2001-01-08

2004-05-25

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000, C713S401000, C713S500000

Reexamination Certificate

active

06742151

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 00-04378, filed on Jan. 28, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device with a scan signal converting circuit for generating plural scan signals in response to scan signals corresponding to one of the scan styles. The plural scan signals are used for embedded circuits adopting various scan styles.
Recently, there have been an increasing number of core-based integrated circuit (IC) designs. This means that the use of system-on-a-chip (SOC) designs is generally recognized as a new design trend. As a result, a memory core or an analog core as well as a central processing unit (CPU) core is frequently used in IC design. In addition, there has been a tendency to invest an IC with plural and various kinds of cores.
In core design, a scan design is often adopted to insure testability. In such a scan design, a scan style is selected to have one of: a multiplexed-scan scan style, a clocked-scan scan style, or a level sensitive scan design (LSSD) scan style. The scan design may also be adopted in a full chip design to insure testability.
In full chip design, if a scan style for an embedded core is different from a scan style for a user defined logic (UDL), it is necessary to convert the test protocol of the core or the UDL to test the chip. An SOC test using automatic test-pattern generation (ATPG) algorithm can be easily performed if shift and normal operation of the core and the UDL is controlled by one of the test protocols.
For the SOC test, a well-prepared core, called a test ready core, provides an efficient test access scheme for the core as well as for the UDL. The test ready core also provides a test isolation capability to prevent any bus conflict during the SOC test. One example of the test ready core is set forth in a paper titled TEST READY CORE DESIGN FOR TEAKLITE CORE, by Heemin Park et al. This paper was published in August, 1999 issue of First IEEE AP-ASIC, pages 363-366. The paper describes a method for testing the UDL and a shadow logic of the core by constructing an isolation ring in the core and using an ATPG algorithm. The isolation ring constructed in the core uses a scan style chosen from: the multiplexed-scan scan style, the clocked-scan scan style, and the LSSD scan style. These scan styles are described in more detail in “Synopsys, Scan Synthesis Reference Manual,” version 2000.05, chapter 3, “Choosing a Methodology and Scan Style,” pages 3-1 to 3-40, published in 2000.
In an SOC test, if the scan style for the core is different from the scan style for the UDL or other embedded core, it can be problematic to convert the test protocols of the core and the UDL to perform the ATPG algorithm. One way to solve this problem is shown in U.S. Pat. No. 5,850,150 to Mitra et al., issued in December, 1998, entitled “FINAL STAGE CLOCK BUFFER IN A CLOCKED DISTRUBUTION NETWORK.” This design employs a buffer that receives an input scan signal and outputs a clock signal and a scan clock signal. In addition, another solution is shown in U.S. Pat. No. 5,783,960 to Lackey, issued in July, 1998, entitled “INTEGRATED CIRCUIT DEVICE WITH IMROVED CLOCK SIGNAL CONTROL,” which uses an LSSD master/slave clock control method and related structure.
Recently, as the number of cores embedded in a given system have increased, the related SOC system has become more complex. Thus, various kinds of scan styles may be used in an SOC system. However, the methods described above are restricted to converting the test protocol from a clocked-scan scan style into a multiplexed-scan scan style, and operate only to control the LSSD clock signal. Therefore, a novel scan signal converting circuit is required that is capable of handling various kinds of scan styles to more easily and effectively test the SOC system.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a scan signal converting circuit for generating a plurality of scan signals for embedded circuits that adopt various scan styles, in response to scan signals corresponding to one particular scan style.
In order to attain the above objects, and according to an aspect of the present invention, a semiconductor integrated circuit is provided that comprises a first logic block adopting a first scan style, having a plurality of first scan cells for testing the semiconductor integrated circuit; a second logic block adopting a second scan style, having a plurality of second scan cells for testing the semiconductor integrated circuit, the second scan style being different from the first scan style; a scan signal converting circuit coupled to the first and second logic blocks, for converting input scan signals for controlling the first logic block into first modified scan signals for controlling the second block, so as to control shift and normal operation of the first and second logic blocks.
Each of the first and second logic blocks is preferably either a core or a user defined logic. The first and second scan styles are preferably chosen from the group of: a clocked-scan scan style, a multiplexed-scan scan style, and a level sensitive scan design (LSSD) scan style.
The semiconductor integrated circuit may further comprise a third logic block adopting a third scan style, having a plurality of third scan cells for testing the semiconductor integrated circuit, the third scan style being different from the first and second scan styles. The scan signal converting circuit is preferably coupled to the third logic block, and converts the input scan signals for controlling the first logic block into second modified scan signals for controlling the third block, so as to control shift and normal operation of the third logic block.
The third logic block is preferably either a core or a user defined logic, and the third scan style is preferably chosen from the group of: a clocked-scan scan style, a multiplexed-scan scan style, and a level sensitive scan design (LSSD) scan style.
In accordance with another aspect of the invention, a semiconductor integrated circuit is provided that comprises a first logic block using a clocked-scan scan style and having a plurality of first scan cells; a second logic block using a multiplexed-scan scan style and having a plurality of second scan cells; a third logic block using a level sensitive scan design (LSSD) scan style and having a plurality of third scan cells; and a scan signal converting circuit coupled to the first through third logic blocks, for generating one or more first scan signals for controlling shift and normal operation of the first logic block, one or more second scan signals for controlling shift and normal operation of the second logic block, and one or more third scan signals for controlling shift and normal operation of the third logic block, all in response to input scan signals for the first logic block, so as to test the integrated circuit under control of the input scan signals.
The scan signal converting circuit preferably comprises: a first scan signal generating means for generating the one or more first scan signals for the first logic block and the one or more second scan signals for the second logic block, in response to the input scan signals; and second scan signal generating means for generating the one or more third scan signals for the third logic block in response to the one or more first scan signals.
The first scan signal generating means preferably comprises: a first delay for generating an output scan clock signal (SCK) for the first logic block, by delaying an input scan clock signal (SCK-IN) included in the input scan signals; a second delay for generating a system clock signal (CK) for the first logic block, by delaying an input system clock signal (CK-IN) included in the input scan signals; a latch circuit for latching the input system clock

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