Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reissue Patent
2007-04-17
2007-04-17
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reissue Patent
active
09871978
ABSTRACT:
A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.
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Hatakenaka Makoto
Tomishima Shigeki
Yamagata Tadato
Yamazaki Akira
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
Ton David
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