Semiconductor integrated circuit device and process for manufact

Details Semiconductor integrated circuit device and process for manufact Semiconductor integrated circuit device and process for manufact

1997-06-23

1999-08-31

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438649, H01L 218234

Patent

active

059465654

ABSTRACT:
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

REFERENCES:
patent: 5656524 (1997-08-01), Eklund et al.
patent: 5716871 (1998-02-01), Yamazaki et al.

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