Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-11-20
2007-11-20
Lamarre, Guy (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C714S739000, C714S744000
Reexamination Certificate
active
10291599
ABSTRACT:
A semiconductor integrated circuit device having a test clock generating circuit enabling a high performance test operation and a method of designing a semiconductor integrated circuit device enabling setting of high precision timing margins is disclosed. A test clock generating circuit having a register sequential circuit and a clock output control circuit is provided between a pulse generating circuit and a logic circuit. When a test operation is active, transfer of a clock pulse generated in the pulse generating circuit to the logic circuit is stopped and a test clock pulse operating the logic circuit is outputted using a pulse signal generated in the pulse generating circuit by controlling a clock transfer control circuit with the sequential circuit depending on setting information of a register. The test clock generating circuit is comprised using a logic design tool utilizing a computer in order to test logic circuit functions and timing margins.
REFERENCES:
patent: 5524114 (1996-06-01), Peng
patent: 6055658 (2000-04-01), Jaber et al.
patent: 6158032 (2000-12-01), Currier et al.
patent: 6418545 (2002-07-01), Adusumilli
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6598192 (2003-07-01), McLaurin et al.
patent: 6671848 (2003-12-01), Mulig et al.
patent: 6738921 (2004-05-01), Lo et al.
patent: 6966021 (2005-11-01), Rajski et al.
patent: 61-042933 (1984-08-01), None
patent: 10-307167 (1997-05-01), None
patent: 11-142478 (1997-11-01), None
Japanese Notification of Reasons for Refusal with English translation, no date.
Japanese Decision of Refusal with English translation, no date.
Date Hisakazu
Ikeya Toyohito
Kawashima Masatoshi
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Hitachi , Ltd.
Lamarre Guy
Reed Smith LLP
LandOfFree
Semiconductor integrated circuit device and method of design... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and method of design..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and method of design... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3873062