Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-03-20

2002-04-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C365S201000

Reexamination Certificate

active

06367044

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device in which a central processing unit (CPU) or a logic circuit, and direct random access memory (DRAM) are mounted on a semiconductor chip, and, more particularly, to a semiconductor integrated circuit device capable of performing burn-in test efficiently, in which a central processing unit (CPU) or a logic circuit, and dynamic random access memory (DRAM) are mounted on a semiconductor chip.
2. Description of the Prior Art
FIG. 6
is a block diagram showing a configuration of a conventional semiconductor integrated circuit device on a semiconductor chip
1
on which a dynamic random access memory (DRAM) is mounted. In
FIG. 6
, the reference number
1
designates a semiconductor chip,
2
denotes a dynamic random access memory (DRAM) mounted on the semiconductor chip
1
,
3
indicates an external terminal group having a plurality of external terminals through which burn-in test patterns are provided from external devices (not shown) to the semiconductor chip
1
and the burn-in test patterns are used for operation test of the DRAM
2
. The reference number
4
designates a wiring group having a plurality of lines through which the received burn-in test patterns are transferred to the DRAM
2
. The reference number
5
denotes input terminal group having a plurality of input terminals of the DRAM
2
. Further, input/output buffers (I/O buffers that are omitted from
FIG. 6
) whose number is corresponding to the number of the external terminals in the external terminal group
3
are formed in the semiconductor chip
1
.
FIG. 7
is a block diagram showing a configuration of another conventional semiconductor integrated circuit device formed on a semiconductor chip
1
on which a central processing unit (CPU) or a logic circuit and a DRAM are mounted. The reference number
6
designates the CPU or the logic circuit and
2
indicates the DRAM. The reference number
7
indicates a wiring group having a plurality of lines through which the CPU or the logic circuit
6
and the DRAM
2
are connected.
Next, a description will be given of the operation of the semiconductor integrated circuit device shown in FIG.
6
.
In general, a burn-in test for the DRAM
2
is the test of a reliability performance measurement in order to detect a life time of the DRAM
2
. When the burn-in test for the DRAM
2
in the configuration of the semiconductor chip
1
shown in
FIG. 6
is performed, burn-in test patterns are inputted through the external terminal group
3
and the I/O buffers (not shown) in the semiconductor chip
1
, and then the received burn-in test patterns are transferred to the input terminal group
5
of the DRAM
2
through the wiring group
4
.
In the conventional semiconductor integrated circuit device shown in
FIG. 6
, after the burn-in test patterns are provided to the DRAM
2
, test results obtained from the DRAM
2
are transferred to external devices through the external terminal group
3
and then the test results are compared with the burn-in test patterns in order to perform the reliability test of the operation of the DRAM
2
.
FIG. 7
shows the configuration of the conventional semiconductor integrated circuit device of a hybrid type in which both the CPU or the logic circuit
6
and the DRAM
2
are mounted on the same semiconductor chip
1
. This hybrid type semiconductor device is becoming one of the leading mainstreams of large scale hybrid integrated semiconductor circuit devices. By using the configuration of the semiconductor integrated circuit device shown in
FIG. 7
, it is possible to avoid a drawback caused in the configuration of an interface between a chip of the CPU or the logic circuit
6
and a chip of the DRAM
2
. On the contrary, the configuration shown in
FIG. 7
has the wiring group
4
having a plurality of lines through which the CPU or the logic circuit
6
are connected to the DRAM
2
electrically. In the prior art, when the burn-in test for the DRAM
2
is performed in the configuration shown in
FIG. 7
, there is a drawback that it is difficult to input burn-in test patterns directly to the DRAM
2
through an external terminal group and corresponding I/O buffers (omitted from
FIG. 7
) and difficult to perform the burn-in test for the DRAM
2
correctly.
As described above, because the conventional semiconductor integrated circuit device has the configuration shown in
FIG. 6
in which only the DRAM
2
is formed on the semiconductor chip
1
, when the burn-in test is performed, it must be required to have the external terminal group
3
, the I/O buffers, and the lines forming the wiring group
4
whose number is corresponding to the number of the input terminals of the DRAM
2
. Accordingly, there is a case that it is difficult to form the dedicated terminals for the burn-in test pattern in the semiconductor chip in configuration.
In addition, according to the development of large scale integrated circuit devices as DRAM
2
, it must be required to form a plurality of dedicated terminals in the external terminal group
3
and I/O buffers only for the test of the DRAM
2
under the limitation of the number of the terminals in the external terminal group
3
and the I/O buffers in the semiconductor chip
1
. In addition to this drawback, in the prior art, there is another drawback that the wiring group
4
requires a larger area in the semiconductor chip
1
under the limitation of the area of the semiconductor chip
1
. Furthermore, because the burn-in test is the reliability test only for the DRAM
2
, not for the CPU, the logic circuit, and the wiring group as component elements other than the DRAM
2
mounted on the same semiconductor chip
1
, it is required to minimize the number of the component elements other than the DRAM
2
. However, a plurality of I/O buffers are formed corresponding to the number of the terminals in the external terminal group
3
, and operate. This causes to add the influence of the defects of the component elements, such as the I/O buffers, other than the DRAM
2
into the test result of the burn-in test only for the DRAM
2
. Thereby, this causes to decrease the accuracy of the reliability of the test result of the burn-in test for the DRAM
2
.
Moreover, the wiring group
7
having a plurality of lines is formed between the CPU or the logic circuit
6
and the DRAM
2
in the conventional hybrid type semiconductor integrated circuit device shown in
FIG. 7
in which the CPU or the logic circuit
6
and the DRAM
2
are mounted on the same semiconductor chip
1
. Accordingly, there is the drawback that when the burn-in test for the DRAM
2
is performed, it is difficult to input burn-in test patterns directly to the DRAM
2
through external terminals and corresponding I/O buffers (omitted from
FIG. 7
) and it is also difficult to perform the burn-in test for the DRAM
2
correctly.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration of the drawbacks of the conventional semiconductor integrated circuit device, to provide a semiconductor integrated circuit device as a hybrid type semiconductor integrated circuit device, in which a CPU or a logic circuit and a DRAM are mounted on a same semiconductor chip, capable of performing a burn-in test for the DRAM without increasing the number of external terminals, I/O buffers, and wiring group in the semiconductor chip.
In accordance with a preferred embodiment of the present invention, a semiconductor integrated circuit device comprises a central processing unit (CPU) or a logic circuit mounted on a same semiconductor chip, a dynamic random access memory (DRAM) mounted on the same semiconductor chip, and a pattern generator for generating burn-in test patterns for the DRAM based on control signals received through external terminals of the same semiconductor chip and for providing the generated burn-in test patterns to input terminals of the DRAM. In the semiconductor integrated circuit device

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2927125