Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-04
2009-10-27
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S030000, C713S320000, C713S324000, C713S340000
Reexamination Certificate
active
07610533
ABSTRACT:
In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.
REFERENCES:
patent: 5311081 (1994-05-01), Donaldson et al.
patent: 5941990 (1999-08-01), Hiiragizawa
patent: 6208170 (2001-03-01), Iwaki et al.
patent: 6225858 (2001-05-01), Guardiani et al.
patent: 6433584 (2002-08-01), Hatae
patent: 6609209 (2003-08-01), Tiwari et al.
patent: 6753702 (2004-06-01), Mizuno et al.
patent: 7102382 (2006-09-01), Drenth et al.
patent: 7124339 (2006-10-01), Sumita et al.
patent: 2004/0004888 (2004-01-01), Sumita et al.
patent: 2006/1023231 (2006-10-01), Nomura
patent: 0284276 (1988-09-01), None
patent: 05-206420 (1993-08-01), None
patent: 2001-015692 (2001-01-01), None
patent: 2001-059856 (2001-03-01), None
patent: 2002-350505 (2002-12-01), None
patent: 2003-098223 (2003-04-01), None
patent: 2003-152082 (2003-05-01), None
patent: 2003-315413 (2003-11-01), None
patent: 2004-055872 (2004-02-01), None
patent: WO 20051008777 (2005-01-01), None
English Translation of JP2002350505 (A) from JPO website. JP2002350505 (A) to Hitachi is listed in IDS filed Mar. 26, 2009.
Japanese Notice of Reasons for Rejection, w/ English translation thereof, issued in Japanese Patent Application No. JP 2005-024149 dated Mar. 10, 2009.
Ishimura Takashi
Takeoka Sadami
McDermott Will & Emery LLP
Panasonic Corporation
Tabone, Jr. John J
LandOfFree
Semiconductor integrated circuit and method for testing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method for testing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method for testing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4129960