Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2000-04-28
2001-08-07
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S009000, C326S014000
Reexamination Certificate
active
06271677
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (hereinafter referred to as “semiconductor IC”) having a circuit structure for detecting whether there is any fault by which a delay in a signal transmission path increases and the IC cannot provide expected performance (delay fault), and a method for testing the semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
In recent years, with increase in integration density of semiconductor ICs, elements and lines constituting the semiconductor ICs have been fined and densified. On the other hand, with increase in processing speed, higher operation frequency is required of the semiconductor ICs.
Consequently, a margin relating to a signal delay which occurs in a signal transmission path between registers as components of a semiconductor IC is reduced and, therefore, it is important to test a manufactured semiconductor IC as to whether it can provide expected performance or not, by detecting the presence of a delay fault in the signal transmission path.
For example, Japanese Published Patent Application No. Hei.5-249186 disclosed a method for testing a logic circuit, in which a test signal generation point and a test signal observation point are provided at the starting point and the end point of a signal transmission path in a semiconductor IC, respectively, to detect the presence of a delay fault in the signal transmission path.
FIG. 10
is a diagram for explaining a conventional method for testing signal transmission paths, schematically illustrating a circuit to be tested in a semiconductor IC, and a tester used for the test.
The semiconductor IC comprises a logic circuit
9003
having a plurality of signal transmission paths, a logic circuit
9001
providing test signal generation points for detecting whether delay faults exist in the signal transmission paths or not, and a logic circuit
9002
providing test signal observation points for detecting whether delay faults exist in the signal transmission paths.
The logic circuit
9001
includes first, second, and third registers (Level Sensitive Scan Design (LSSD))
91
,
92
, and
93
each comprising a master latch L
1
and a slave latch L
2
, and these registers
91
~
93
are used as shift registers when performing the test. The register
91
serves as a generation point of a test signal for detecting whether delay faults exist in the signal transmission paths in the logic circuit
9003
, and the registers
92
and
93
serve as generation points of signals for activating target signal transmission paths to be tested. The test signal generated by the register
91
is output to the target signal transmission paths activated by the signals from the registers
92
and
93
.
Likewise, the logic circuit
9002
includes first, second, and third registers (LSSD)
94
,
95
, and
96
each comprising a master latch L
1
and a slave latch L
2
, and these registers
94
~
96
serve as observation points for observing the test signal transmitted through the target signal transmission paths, thereby detecting whether delay faults exist in the signal transmission paths in the logic circuit
9003
.
In
FIG. 10
, SYS data is data in a normal operation mode, and this SYS data is latched into the register L
1
by a clock A. Further, a scan data input (test signal) is latched into the register L
1
by a clock C
1
. Further, data from the register L
1
is latched into the register L
2
by a clock C
2
.
The tester
9100
outputs the clocks C
1
and C
2
at predetermined timings, and decides whether the target signal transmission paths have passed the test or not. To be specific, a signal which is set in the logic circuit
9001
from the scan data input by scanning is changed, influence of this change is observed by the logic circuit
9002
, the signal received at the logic circuit
9002
is output to the scan data output b by scanning, and the output value is compared with an output value which has previously been obtained in a normal circuit.
In the above-described method using the conventional test circuit, changes of the test signals generated in the registers
91
~
93
(test signal generation points) are latched by the registers
94
~
96
(test signal observation points) after one system clock cycle, and the changes of the test signals at the observation points are compared with the changes of the test signals at the generation points, thereby deciding whether delay faults which affect the performance of the IC exist in the signal transmission paths.
In the conventional method, however, as the number of the signal transmission paths included in the logic circuit
9003
increases, the number of the target signal transmission paths to be tested, which connect the registers serving as the test signal generation points with the registers serving as the test signal observation points, also increases.
Hereinafter, increase in the number of the target signal transmission paths to be tested will be described using a test circuit
900
shown in FIG.
11
.
The test circuit
900
shown in
FIG. 11
comprises a logic circuit
900
a
having signal transmission paths to be tested, a register
9017
forming a test signal generation point which generates a test signal to be input to the logic circuit
900
a
, and a register
9018
forming a test signal observation point which observes the test signal output from the logic circuit
900
a
. The register
9017
corresponds to the register
91
shown in
FIG. 10
, and the register
9018
corresponds to the register
94
shown in FIG.
10
.
The logic circuit
900
a
comprises a logic element
9016
forming a re-convergence point at which the test signal re-converges, partial paths
9010
,
9011
, and
9012
which are positioned between the logic element
9016
and the test signal generation point
9017
, and partial paths
9013
,
9014
, and
9015
which are positioned between the logic element
9016
and the test signal observation point
9018
.
In this test circuit
900
, the signal transmission path branches into the three partial paths
9010
,
9011
, and
9012
at the register
9017
serving as the test signal generation point, and these three partial paths re-converge at the logic element
9016
. Further, the signal transmission path branches into the three partial paths
9013
,
9014
, and
9015
at the logic element
9016
serving as the re-convergence point, and these paths converge again at a point just before the test signal observation point
9018
. Generally, signal transmission lines and combinational logic elements exist in the partial paths and the logic element serving as the re-convergence point, these are omitted in
FIG. 11
to simplify the description.
By the way, although the number of the partial paths positioned between the test signal generation point and the test signal observation point is only six (
9010
~
9015
), the number of the signal transmission paths formed between the generation point and the observation point is equal to the number of combinations of the partial paths between the generation point and the logic element and the partial paths between the logic element and the observation point.
To be specific, in the test circuit, there are nine (first to ninth) signal transmission paths as follows.
That is, the first path comprises the partial path
9010
, the logic element
9016
, and the partial path
9013
. The second path comprises the partial path
9010
, the logic element
9016
, and the partial path
9014
. The third path comprises the partial path
9010
, the logic element
9016
, and the partial path
9015
. The fourth path comprises the partial path
9011
, the logic element
9016
, and the partial path
9013
. The fifth path comprises the partial path
9011
, the logic element
9016
, and the partial path
9014
. The sixth path comprises the partial path
9011
, the logic element
9016
, and the partial path
9015
. The seventh path comprises the partial path
9012
, the logic element
9016
, and the partial path
9013
. The eighth path comprises the partial path
9012
, th
Hosokawa Toshinori
Ichikawa Osamu
Ohta Mitsuyasu
Takeoka Sadami
Matsushita Electric Industrial Company Limited
Tokar Michael
Tran Anh Q.
Wenderoth , Lind & Ponack, L.L.P.
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