Semiconductor integrated circuit and method for testing memory

Details Semiconductor integrated circuit and method for testing memory Semiconductor integrated circuit and method for testing memory

1999-12-15

2001-05-15

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06233182

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a technique for diagnosing a semiconductor integrated circuit (IC) and a technique effective for application to a technique for detecting defective bits in a semiconductor memory. The present invention relates to, for example, a technique effective for use in a semiconductor integrated circuit in which a semiconductor memory, and a test circuit for the semiconductor memory, i.e., a test pattern generator for generating each test pattern are incorporated.
BACKGROUND ART
A system for diagnosing a semiconductor memory such as a semiconductor memory device or the like is carried out by a test device called “memory tester”. The memory tester generates test pattern data, and supplies the test pattern data to a semiconductor memory to be tested to thereby write the data into the corresponding memory cell of the semiconductor memory. Thereafter, the data written into the memory cell is read into the memory tester, and the read data and an expected value held within the memory tester are compared, whereby the semiconductor memory is diagnosed.
A procedure for developing a semiconductor memory is performed as shown in FIG.
11
. The design of a system is carried out based on specifications of the semiconductor memory to be developed. Further, specific circuit design is performed based on the system design. Various photomasks necessary for the fabrication of the semiconductor memory are produced. Thereafter, a wafer having a plurality of semiconductor memory circuits formed thereon is manufactured through a wafer process in a semiconductor manufacturing process by utilizing the photomasks, and the wafer is cut to a plurality of memory chips. Further, the respective memory chips are sealed with a sealing agent such as a resin, so that they are assembled into a package. A sample (also called “sample chip”) is suitably extracted from the semiconductor memories assembled as the package, and the extracted sample is inspected by using the memory tester. Thus, the presence or absence of a faulty component lying within the sample can be detected.
When the faulty component is found out, the result of testing on the sample regarded as the faulty component is analyzed to find out the cause of the failure. In order to avoid the failure, redesign such as system design, circuit design or layout design or the like for the semiconductor memory is carried out. A wafer formed with a plurality of semiconductor memory circuits is manufactured again through the wafer process in the semiconductor fabricating process, based on the redesigned data. The execution of a retest is repeated by the memory tester. The development of the semiconductor memory has been regarded as completed at a stage in which no failure is detected upon testing.
However, in the diagnostic system for supplying the test pattern data generated from the memory tester to the corresponding semiconductor memory as described above, various semiconductor integrated circuit devices (also called “IC”) constituting the tester have been manufactured by a manufacturing or production processing technique antecedent to one generation or a few generations as compared with the generation of each semiconductor memory to be checked. Namely, the minimum values of the fabrication processing dimensions of the respective semiconductor integrated circuit devices constituting the tester are set thicker than those of the semiconductor memory to be checked. Thus, a next-generation or new-generation semiconductor memory is checked or examined by the memory tester comprised of the previous-generation semiconductor integrated circuit devices. Therefore, specifications such as an operating speed, etc. necessary for a memory tester for examining the new-generation semiconductor memory would become very strict. In order to achieve a desired test speed, a plurality of semiconductor integrated circuits respectively having the same function are prepared within the memory tester. A contrivance to make the test speed faster is made by, for example, constructing a system so that the semiconductor integrated circuits can be parallel-processed. As a result, the memory tester is accompanied by a problem that the system becomes complex in configuration and the size thereof would become inevitably large.
In a logic semiconductor integrated circuit device or the like on the other hand, a logic simulation using a work station is performed at a stage of circuit design and system design prior to a wafer process in a semiconductor manufacturing process and wafer fabrication. Further, a technique for detecting failures in advance has been established. Therefore, the test procedure of the logic semiconductor integrated circuit device has an advantage in that the total interval required to develop it would become short as compared with the test procedure of the aforementioned semiconductor memory, for manufacturing each semiconductor chip (also called “real chip”) corresponding to an actual product and testing it.
However, since test patterns necessary for a logic simulation are different from each other every logic semiconductor integrated circuit device, much time is required to form the test patterns. Further, there is also inconvenience that since the test patterns are long in the number of steps, the time required to test the real chip becomes long as compared with the test on the real chip by the tester, thereby making it impossible to substantially execute the test.
There may be cases where in the semiconductor memory on the other hand, the numbers of bits of addresses and data simply differ from each other even in the case of the development of a new product and thereby most of generation programs for test patterns do not stand in need of changes. There may be also cases in which the know-how to analyze failures, which has been built up till now, can be utilized. Therefore, it has been tested by the memory tester after the sample chip has been manufactured as described above.
However, the above-described development procedure has a problem in that although the load on the design is small, the time required between redesigning the memory circuit and fabricating the chip once a failure occurs, greatly increases, so that the period for the development of the semiconductor memory would become long.
Further, the above-described developing system has a problem in that since the recent semiconductor memory is complex in its timing condition from a demand for speeding up and a demand for the achievement of an increased or advanced function such as a pipeline operation as in the case of a synchronous dynamic random access memory (hereinafter also called “SDRAM”), a mistake in its design increases and the period for its development becomes long increasingly.
On the other hand, a verifying tool, which has allowed the generation of a test pattern matched with a product's operation with an operating level from an EDA (Engineering Design Automation) bender, has been announced. One example thereof is a verifying tool called “VisualTest” by TSSI Co., Ltd. In the present verifying tool, a procedure for generating each test pattern is inputted in flowchart form by using a workstation or the like, whereby a semiconductor memory represented by circuit design data can be checked. A memory development procedure at the time that the present verifying tool is used, is illustrated in FIG.
12
. Incidentally,
FIG. 12
has been considered by the present inventors and is not known to date.
As shown in
FIG. 12
, verification is made using the present verifying tool without fabricating a wafer so that a failure or defect can be detected, whereby an advantage is brought about in that the development period can be greatly reduced.
However, the above-described method needs to create a test pattern as a pattern data file because the verifying tool is a logic verifying tool (logic simulator) called “Verilog” even if an operating level could be described on “VisualTest”. Since the test pattern for the semiconductor memory is massive (ranges from a few giga ste

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