Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-31
2007-07-31
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S030000, C714S700000, C714S707000, C714S716000, C714S731000, C714S734000, C714S744000, C713S500000, C375S371000, C327S158000, C702S106000
Reexamination Certificate
active
11001155
ABSTRACT:
A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.
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Kushiyama Natsuki
Urakawa Yukihiro
Lamarre Guy
Trimmings John P
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