Semiconductor fabrication process including an SiGe rework...

Details Semiconductor fabrication process including an SiGe rework... Semiconductor fabrication process including an SiGe rework...

2011-06-07

2011-06-07

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21619

Reexamination Certificate

active

07955936

ABSTRACT:
A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

REFERENCES:
patent: 7250085 (2007-07-01), Abbadie et al.
patent: 7335545 (2008-02-01), Currie
patent: 2007/0161196 (2007-07-01), Currie et al.

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