Semiconductor fabrication employing self-aligned sidewall spacer

Details Semiconductor fabrication employing self-aligned sidewall spacer Semiconductor fabrication employing self-aligned sidewall spacer

1997-10-24

1999-01-12

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438275, 438289, H01L 21336

Patent

active

058588485

ABSTRACT:
A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate. A dielectric, preferably nitride, is deposited by CVD across the exposed LDD areas of the semiconductor substrate, the sacrificial dielectric, and the gate conductor. The nitride is removed down to a plane level with the upper surface of the gate conductor. The sacrificial dielectric may then be removed from the semiconductor substrate. An ion implantation which is self-aligned to exposed lateral edges of the spacers may then be performed to form heavily doped source/drain regions laterally spaced from the channel.

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patent: 5374574 (1994-12-01), Kwon
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patent: 5534447 (1996-07-01), Hong
patent: 5597752 (1997-01-01), Niwa

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