Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2011-03-08
2011-03-08
Tran, Minh-Loan T (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S621000, C257S685000, C257S686000, C257S698000, C257S777000, C257SE23067, C257SE23068, C257SE23085, C257SE23174, C257SE23178, C257S072000, C257SE21577, C257SE21599, C257SE21705, C257SE23011, C438S109000, C438S462000
Reexamination Certificate
active
07902638
ABSTRACT:
A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.
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Chua Linda Pei Ee
Do Byung Tai
Kuan Heap Hoe
Atkins Robert D.
Lopez Fei Fei Yeung
Patent Law Group
STATS ChipPAC Ltd.
Tran Minh-Loan T
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