Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-11
2009-06-02
Tu, Christine T (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S815000, C713S401000
Reexamination Certificate
active
07543201
ABSTRACT:
A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values be different. Related methods are also discussed.
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Notice of Allowability issued for Korean Application No. 10-2005-0076986 on May 10, 2007.
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
Tu Christine T
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