Semiconductor device with programmable impedance control...

Details Semiconductor device with programmable impedance control... Semiconductor device with programmable impedance control...

2005-01-04

2005-01-04

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189070

Reexamination Certificate

active

06839286

ABSTRACT:
An output impedance control circuit of a semiconductor device. A first transistor is connected to a pad and a level controller controls a gate voltage of the first transistor in response to a voltage of the pad and a reference voltage. A MOS array is connected between the pad and a power supply voltage and supplies current to the pad in response to an impedance control code. A first control circuit generates the impedance control code in response to whether a voltage of the pad is converging to the reference voltage. A second control circuit controls a pull-up impedance of the output buffer circuit in response to the first impedance control code when a voltage of the pad is converging to the reference voltage.

REFERENCES:
patent: 6573746 (2003-06-01), Kim et al.
patent: 2001-0050550 (2001-06-01), None

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