Semiconductor device with improved overlay margin and method...

Details Semiconductor device with improved overlay margin and method... Semiconductor device with improved overlay margin and method...

2010-04-29

2011-10-11

Nguyen, Dao (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S196000, C438S238000, C438S243000, C438S259000, C438S270000, C438S391000, C257S296000, C257S297000, C257S306000, C257S314000, C257S315000, C257S324000, C257S368000, C257SE21657, C257SE21658, C257SE21585, C257SE27088

Reexamination Certificate

active

08034684

ABSTRACT:
Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

REFERENCES:
patent: 6984863 (2006-01-01), Miida
patent: 7732279 (2010-06-01), Park

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