Semiconductor device testing apparatus

Details Semiconductor device testing apparatus Semiconductor device testing apparatus

2001-05-23

2004-01-13

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

06678852

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing, for example, various semiconductor devices such as semiconductor memories or logic ICs with memories mounted.
2. Description of the Related Art
FIG. 4
shows an outline of a conventional semiconductor device testing apparatus.
FIG. 4
shows a configuration depicted by paying an attention only to signal paths in the testing apparatus. A pattern generating part
11
outputs signals or data such as an X address signal XAD, a Y address signal YAD, first and second device control signals MUS
1
and MUS
2
, a test pattern data TP containing an expected value data EX, and the like which are to be applied to a semiconductor device under test
10
.
A programmable data selecting part
12
classifies those signals or data in accordance with specifications of each pin of the semiconductor device under test
10
, and allocates those signals to corresponding channels in the semiconductor device testing apparatus.
An input signal cycle delaying part
13
gives each signal a delay that agrees with the specifications of each input pin of the semiconductor device under test
10
, and further adjusts its voltage level and pulse width in accordance with the specification conditions to supply the delayed and adjusted signal to the semiconductor device under test
10
as an input signal SIN.
On the other hand, an expected value data EX allocated to an expected value data channel by the programmable data selecting part
12
is supplied to a logical comparison part
15
through an expected value data transmission path
17
as an expected value data EX after a delay that agrees with output specifications of the semiconductor device under test
10
is given thereto by an expected value data cycle delaying part
14
.
The logical comparison part
15
compares a response output signal SOUT outputted from the semiconductor device under test
10
with an expected value data EX given through the expected value data transmission path
17
. When a discordance occurs in the comparison, for example, a logical “1” representing a failure is set in a bit position where the discordance occurred, and failure data FL
10
, FL
11
, FL
12
, - - - each being able to specify a failure cell position based on this failure bit position are outputted from the logical comparison part
15
.
Each of the failure data FL
10
, FL
11
, FL
12
, - - - is inputted to a data failure memory
16
, and the data failure memory
16
is switched to writing mode by the input of each of the failure data FL
10
, FL
11
, FL
12
, - - - . An X address signal XAD, a Y address signal YAD, first and second device control signals MUS
1
and MUS
2
, and a test pattern data TP containing an expected value data EX outputted from the pattern generating part
11
at a time point when each of the failure data FL
10
, FL
11
, FL
12
, - - - is generated are acquired and stored in the data failure memory
16
via a data transmission path
18
without any time delay.
Here, types of failure memories to be mounted in a semiconductor device testing apparatus will briefly be explained below. There are two types of failure memories each being to be mounted in a semiconductor device testing apparatus. One of the two types is an address failure memory that has the same address area as that of the semiconductor device under test, and the other is a data failure memory that stores therein failure data, address data, and test pattern data.
An address failure memory requires a large memory capacity since it has the same address area as that of the semiconductor device under test. That is, memory capacity is becoming larger and larger every year, and if the number of semiconductor devices tested at the same time becomes larger from, for example, current 32 to 64 or 128 etc., there is a drawback, in an address failure memory, that the same number of failure memories as the number of semiconductor devices under test must be mounted on a testing apparatus, and therefore the cost of the mounted failure memories becomes extremely high.
On the contrary, if the number of failure occurrences is small, failure memory capacity of a data failure memory may be small. Therefore, in order to provide a less expensive semiconductor device testing apparatus, a semiconductor device testing apparatus of a type on which a data failure memory
16
is mounted is advantageous.
From such a background, a semiconductor device testing apparatus on which a data failure memory is mounted is used in many cases. However, data to be stored in the data failure memory
16
are an X address signal XAD, an Y address signal YAD, a test pattern data TP, and the like outputted from the pattern generating part
11
at a time when a failure is detected. Therefore, since an address where a failure occurred, a test cycle when a failure occurred, or the like are to be estimated from these data, there is a drawback that it takes a longer time and more workload for a failure analysis.
This situation will be explained below using FIG.
5
. The indication A in
FIG. 5
shows an X address signal XAD, an Y address signal YAD, a test pattern data TP, and first and second device control signals MUS
1
and MUS
2
outputted from the pattern generating part
11
.
An X address signal XAD outputted from the pattern generating part
11
is supplied to the semiconductor device under test
10
as a row address signal ROW
1
, and a Y address signal YAD is supplied to the semiconductor device under test
10
as one of column address signals COL
10
, COL
11
, COL
12
, COL
13
, - - - .
In addition, in this example, there is shown a case where a read command READ is applied, as the second device control signal MUS
2
, to each of four addresses (ROW
1
, COL
10
; ROW
1
, COL
11
; ROW
1
, COL
12
; ROW
1
, COL
13
) to be accessed by the row address ROW
1
and the column addresses COL
10
-COL
13
. Further, as the first device control signal MUS
1
, is applied a control signal ACT for directing the semiconductor device under test l
0
to acquire a row address. In addition, EX
10
, EX
11
, EX
12
, EX
13
, - - - are expected value data that are logically compared respectively with response output signals RD
10
, RD
11
, RD
12
, RD
13
, - - - (refer to
FIG. 5B
) outputted from the semiconductor device under test
10
in accordance with the read command READ.
Those signals outputted from the pattern generating part
11
are delayed, if each of their output timings (t=0) is referred to as an initial timing of each signal, by the input signal cycle delaying part
13
and the expected value data cycle delaying part
14
shown in
FIG. 4
to the state shown in B and C of
FIG. 5
, and are inputted to the semiconductor device under test
10
and the logical comparison part
15
through their corresponding transmission paths.
That is, each of the address signals COL
10
, COL
11
, COL
12
, COL
13
, - - - to be applied to the semiconductor device under test
10
is delayed by two test cycles (t=2&tgr;) from its initial timing (t=0) at which the corresponding row address signal ROW
1
is applied, and then is supplied to the semiconductor device under test
10
. This time delay is determined by a characteristic of the semiconductor device under test
10
. Moreover, there is shown a case in which each of the read command signals READ is also delayed by two test cycles, and is applied to the semiconductor device under test
10
.
In addition, in this example, there is shown a case in which each of the response output signals RD
10
, RD
11
, RD
12
, RD
13
, - - - of the semiconductor device under test
10
is delayed by three test cycles from a timing at which the corresponding read command signal READ is applied, and is outputted (refer to B of FIG.
5
).
Therefore, each of the response output signals RD
10
, RD
11
, RD
12
, RD
13
, - - - is outputted at a timing delayed by five test cycles (t=5&tgr;) from its output initial timing of the pattern generating part
11
.
For this reason, each o

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