Semiconductor device tested using minimum pins and methods...

Details Semiconductor device tested using minimum pins and methods... Semiconductor device tested using minimum pins and methods...

2006-02-02

2009-08-11

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000

Reexamination Certificate

active

07574638

ABSTRACT:
The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in response to an external reset signal and a clock signal, an operation mode storage for receiving serial data synchronized with the clock signal through the test pin in response to the enable signal, and an operation mode decoder for generating operation mode selection signals in response to the serial data stored in the operation mode storage. Another semiconductor device comprises an input/output pin for receiving test data, a delay reset signal generator for delaying a reset signal, a counter for counting a clock signal in response to the reset signal to generate a counted value, a mode register for storing the test data, and a decoder for generating selection signals to the mode register to designate a position in the mode register where the test data is written.

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