Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-05
2001-07-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000
Reexamination Certificate
active
06261909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method for making a semiconductor device having very shallow junctions and a short channel length.
2. Description Of The Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. The speed at which integrated circuit devices, e.g., transistors, operate may be determined, in part, by the channel length of the transistor device. All other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the channel length of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
The ability to reduce the channel length, or feature size, of modern transistors is presently limited by modern photolithography equipment and techniques. Traditionally, components of a transistor, such as the gate conductor and gate dielectric, are made by forming the appropriate process layers, e.g., silicon dioxide and polysilicon, above the surface of a semiconducting substrate, forming a layer of photoresist above the layer of polysilicon, developing and patterning the layer of photoresist to define a mask that covers what will become the gate conductor and gate oxide, and removing the portions of the polysilicon and silicon dioxide layers that extend beyond the mask through one or more etching steps.
Using the traditional photolithography techniques described above, the feature size, e.g., the width of the gate conductor, is a result of directly forming the feature size in a layer of photoresist, or other similar masking layer, above the semiconducting substrate. To achieve further reductions in the feature size of transistors, e.g. the channel length, it may be useful to develop an alternative method that will allow formation of transistors with feature sizes smaller than that achievable with current photolithography techniques.
The present invention is directed to a method of making a semiconductor device that minimizes or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of making a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating those features. The method comprises forming a first process layer above a semiconducting substrate, forming a second process layer comprised of an oxidation resistant material above the first process layer, and defining a first opening in the first and second process layers. The method continues with the oxidation of the substrate lying within the first opening, to thereby form a third process layer, defining a second opening in the third process layer, and forming a plurality of sidewall spacers in at least the second opening. The method concludes with the formation of a gate dielectric above the surface of the substrate between the sidewall spacers, forming a gate conductor above the gate dielectric, and forming a plurality of source/drain regions in said substrate.
The transistor is comprised of a substrate having a recess formed therein, and a gate dielectric positioned above the substrate lying within the recess, the gate dielectric and the substrate defining an interface that is positioned beneath the surface of the substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent at least the gate conductor, and a plurality of source/drain regions formed in the substrate.
REFERENCES:
patent: 5908313 (1999-06-01), Chau et al.
patent: 5963800 (1999-10-01), Augusto
patent: 6096641 (2000-08-01), Kunikiyo
patent: 6107144 (2000-08-01), Jang et al.
Fulford H. Jim
Gardner Mark I.
May Charles E.
Advanced Micron Devices, Inc.
Nelms David
Nhu David
Williams Morgan & Amerson P.C.
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