Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-16
2004-01-27
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000
Reexamination Certificate
active
06683354
ABSTRACT:
RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-12603, filed on Mar. 12, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a fabrication method therefor, and more particularly, to a semiconductor device having a trench isolation layer and a fabrication method therefor.
BACKGROUND OF THE INVENTION
As integration density of semiconductor memory devices (e.g., DRAMs) increases, circuit components such as transistors are formed closer to each other and reliability of the devices decreases unless effective isolation techniques for separating devices such as MOS transistors next to each other are employed. Trench isolation techniques which can form an isolation region having a narrow width are widely used in the manufacture of highly integrated semiconductor memory devices. Other conventional isolation methods include local oxidation of silicon (LOCOS).
However, as integration density of the semiconductor memory device increases, the width of the trench in which the isolation layer is formed is also diminished. Therefore, an effective method of filling the trench without a void or a seam is needed.
Silicon oxide is commonly used as trench filing material. Various methods for forming an oxide layer, which has relatively good gap filling properties, are proposed for filling a trench having high aspect ratio. One of the methods by use of a silicon oxide composed of TEOS (Tetra Ethyl Ortho Silicate)-USG (Undoped Silicate Glass) or a silicon oxide composed of HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) is suggested. However, such a method is not suitable for filling a trench having a very high aspect ratio, e.g., a width of about 1200 Å and a depth of about 6000 Å.
Another known method for filling a trench is using a Spin-on-Glass (SOG) layer. SOG is a liquid state or a sol state in the first time, therefore, gap filling characteristics are excellent and step differences are reduced. But it is difficult for the SOG layer to change into a perfect oxide silicon layer, even though a recovery process for changing the SOG layer into an oxide silicon layer is performed through successive heat treatment. A disadvantage of use of a SOG layer is that it is easily removed during an etching process or a cleaning process, because the SOG layer does not have a compact structure. In the case of an organic SOG layer, heat treatment is difficult, and organic components which remain may affect semiconductor device operations. Also, shrinkage may occur after coating. Consequently, a crack may form in the SOG layer during heat treatment after forming the layer, and a stress difference is generated by thermal expansion in accordance with partial recovery states, resulting in a device which may be prone to crack or become defective.
Accordingly, a need exists for a semiconductor device having a trench isolation layer and a fabrication method to reduce defects of the SOG layer.
SUMMARY OF THE INVENTION
A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer.
Preferably, the first buried layer includes an SOG (Spin On Glass) layer, the second buried layer is an HDP-CVD (High Density Plasma Chemical Vapor Deposition) oxide layer. The silicon oxide liner includes an HTO (High Temperature Oxide) layer densified at a temperature over 800° C. The silicon oxide liner in an upper part of the trench isolation layer is thinner than a lower part of the silicon oxide liner. An upper surface of the first buried layer is recessed about 1000 Å from the upper surface of the semiconductor substrate.
A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.
A method of forming a trench isolation layer of a semiconductor device is also provided which includes the steps of: forming a trench-etching pattern for defining an active area on a substrate; forming an isolation trench on the substrate using the trench etching pattern as an etching mask; forming a silicon nitride liner on an inner wall of the trench; forming a silicon oxide liner on an inner side of the silicon nitride liner; performing heat treatment for hardening the silicon oxide liner; partially filling the trench having the silicon oxide liner with a first buried layer; partially recessing an upper surface of the first buried layer by etching; and filling the trench by depositing the second buried layer on the first buried layer whose upper surface is partially recessed.
The method preferably further includes a step of forming a thermal oxide layer on the inner wall of the trench, between the step of forming the trench and the step of forming the silicon nitride layer. And the method preferably further includes the steps of: exposing an upper part of the trench etching pattern, by removing the second buried layer with a planarization etching; and selectively removing the trench etching pattern.
According to a preferred embodiment of the present invention, the silicon oxide liner includes an HTO oxide layer, and the heat treatment is performed over about 1100° C. for about 30 minutes to about 90 minutes. The step of filling the first buried layer includes an SOG layer, and a curing step for changing the SOG layer into a silicon oxide layer is further included, before the step of etching the first buried layer. The SOG layer includes a polysilazane series material, and the curing step is performed at a temperature of about 700° C. to about 800° C. for about 10 minutes to about 60 minutes. The step of depositing the second buried layer includes HDP-CVD. The step of etching the first buried layer is processed by wet etching.
REFERENCES:
patent: 4631803 (1986-12-01), Hunter et al.
patent: 5435888 (1995-07-01), Kalnitsky et al.
patent: 5801083 (1998-09-01), Yu et al.
patent: 6187651 (2001-02-01), Oh
patent: 6194283 (2001-02-01), Gardner et al.
patent: 6228742 (2001-05-01), Yew et al.
patent: 6258697 (2001-07-01), Bhakta et al.
patent: 6333218 (2001-12-01), Ngo et al.
patent: 6339004 (2002-01-01), Kim
patent: 6391738 (2002-05-01), Moore
Heo Jin-Hwa
Hong Soo-Jin
Blum David S
F. Chau & Associates LLP
Jr. Carl Whitehead
Samsung Electronics Co,. Ltd.
LandOfFree
Semiconductor device having trench isolation layer and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having trench isolation layer and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having trench isolation layer and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3246305