Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-25
2003-12-02
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000, C438S427000, C438S435000
Reexamination Certificate
active
06656783
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an isolation layer and a manufacturing method thereof, and more particularly, to a semiconductor device having a shallow trench isolation structure and a manufacturing method thereof.
2. Description of the Related Art
With the advancement of semiconductor device manufacturing techniques, the speed and integration of semiconductor devices has improved. In addition, small, high-density patterns have been increasingly required. Wide isolation regions in semiconductor devices also require small high density patterns.
Local oxidation of silicon (LOCOS) oxide layers have been mainly used as conventional isolation layers of semiconductor devices. However, bird's beak configurations are created at the edges of the isolation layers by the LOCOS method and thus the area of active regions is reduced, and current leakage occurs.
Presently, shallow trench isolation (STI) layers having narrow widths and excellent isolation characteristics are widely used.
Referring to
FIG. 1
, a blocking pattern (not shown) is formed on a semiconductor substrate
10
to expose an isolation region. The semiconductor substrate
10
is defined as a cell area, a core area and a peripheral area. In addition, the blocking pattern may be a stack layer comprising an oxide layer and a silicon nitride layer. The exposed semiconductor substrate
10
is etched to a predetermined depth using the blocking pattern as a mask, thereby forming trenches t
1
and t
2
therein. Herein, the trench t
1
may be formed in the cell area and the trench t
2
may be formed in the core and peripheral areas. The etching process for forming the trenches t
1
and t
2
is performed by a dry etching method using a plasma.
The dry etching process for forming the trenches t
1
and t
2
may cause silicon lattice defects and damage to the inner surfaces of the trenches t
1
and t
2
. Conventionally, to reduce silicon lattice defects and damage, a sidewall oxide layer
12
is formed by thermally oxidizing the inner surfaces of the trenches t
1
and t
2
. At this time, the sidewall oxide layer
12
is formed to a thickness of only 50 to 100A. Also, the formation of the sidewall oxide layer
12
helps the removal of sharp upper and lower corners of the trenches t
1
and t
2
.
Afterwards, a silicon nitride liner
14
is formed on the surface of the sidewall oxide layer
12
. The silicon nitride liner
14
, as is well known, prevents the generation of stress due to a difference in thermal expansive coefficients of the semiconductor substrate
10
made of silicon and a silicon oxide layer that will be filled into the trenches t
1
and t
2
.
A dielectric material, for example, a high density plasma (hereinafter, referred to as “HDP”) oxide layer is deposited over the resultant semiconductor substrate
10
to fully fill the trenches t
1
and t
2
. Next, chemical mechanical polishing (hereinafter, referred to as “CMP”) is performed on the HDP oxide layer and the blocking pattern to expose the surface of the semiconductor substrate
10
, thereby filling the trenches t
1
and t
2
with the HDP oxide layers. Consequently, a shallow trench isolation (STI) layer
16
is completed.
However, forming the thin and uniform sidewall oxide layer
12
causes the following problems. With reference to
FIGS. 2A and 2B
, since hot carriers of a highly integrated semiconductor MOS transistor generally have high energy, they bounce to a thin gate oxide layer
22
or easily penetrate through the sidewall oxide layer
12
into the STI layer
16
. Herein, the hot carriers penetrating into the STI layer
16
are mainly negative electric charges, namely, electrons
100
, which are easily trapped in the silicon nitride liner
14
and on the interface between the silicon nitride liner
14
and the sidewall oxide layer
12
. The electrons
100
are densely trapped since the sidewall oxide layer
12
is remarkably thin as mentioned above. If the electrons
100
are densely concentrated around the edge of the STI layer
16
, positive electric charges in semiconductor substrate
10
on which MOS transistors are formed, namely, holes
12
are gathered in the periphery of the STI layer
16
. At this time, since the electrons
100
are densely trapped in the silicon nitride liner
14
and on the interface between the silicon nitride liner
14
and the sidewall oxide layer
12
, the holes
12
in the semiconductor substrate
10
are densely gathered together.
Herein, as shown in
FIG. 2A
, since in an N-channel field effect transistor (N-FET) the major carriers are the electrons
100
, a path is not formed between n-type junction areas
26
a
and
26
b
in which the electrons
100
function as major carriers, even though the holes
102
are dense in the periphery of the STI layer
16
.
Because in a P-channel field effect transistor (P-FET) the major carriers are the holes
102
, as shown in
FIG. 2B
, the holes
102
densely arranged at the periphery of the STI layer
16
function as a current path I connecting p-type junction areas
28
a
and
28
b
isolated by the STI layer
16
. Consequently, due to the current path I, although p-type junction areas
28
a
and
28
b
are isolated by the STI layer
16
, leakage current, such as abnormally increased standby current after bum-in, is generated between adjacent P-FETs, thereby deteriorating the device characteristics of the P-FETs. Herein, a reference numeral
24
denotes a gate electrode of a MOSFET.
Furthermore, in a case where a P-FET is on the interface between the STI layer
16
and an active region (hereinafter, referred to as “interface”), a channel area of the P-FET (not shown) is opposite to the silicon nitride liner
14
where the electrons are trapped. Here, the thin sidewall oxide layer
12
is interposed between the channel area of the P-FET and the silicon nitride liner
14
. Consequently, the electrons trapped in the silicon nitride liner
14
easily induce holes in the channel area of the P-FET on the interface. And, the holes induced in turning on the P-FET are not easily removed and remain after turning off the P-FET. Due to this, the length of the channel of the P-FET on the interface is gradually reduced, thereby changing the threshold voltage. Consequently, the characteristics of the P-FET are changed.
To solve the above problems of the P-FET, techniques for increasing the entire thickness of the sidewall oxide layer
12
have been proposed. However, if the entire thickness of the sidewall oxide layer
12
is increased, oxidants easily penetrate into the sidewall oxide layer
12
. Due to the penetration of such oxidants, stress in the N-FET in the cell area connected to a storage capacitor is increased thereby sharply reducing data retention time of the storage capacitor, namely, refresh time. Consequently, the characteristics of a DRAM device are deteriorated.
In summary, if the sidewall oxide layer
12
of the STI is formed to a uniform thickness throughout the entire area, which does not generate abnormally increased standby current after burn-in in the P-FET, then the standby current after burn-in of the P-FET as well as the data retention time of the storage capacitor in the cell area is reduced. If the sidewall oxide layer of the STI is formed to a uniform thickness throughout the entire area, which maintains moderate data retention time of a DRAM device, then the data retention time of the DRAM is maintained while serious abnormally increased standby current after burn-in is generated in the P-FET. Consequently, it is difficult to maintain the characteristics of the P-FET.
Consequently, if sidewall oxide layers in their respective areas are formed to a uniform thickness, it is difficult to simultaneously maintain the excellent device characteristics of the N-FET in the cell area and of the P-FET in the core and periphery areas.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a semiconductor device having a shallow trench isolation (
Marger & Johnson & McCollom, P.C.
Quach T. N.
Samsung Electronics Co,. Ltd.
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