Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-03-20
2003-05-06
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S201000
Reexamination Certificate
active
06560147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital circuit having a scan test circuit and, in particular, to a semiconductor device incorporating the scan test circuit.
2. Description of the Related Art
A scan-path testing method is known as a test facilitating technique for a semiconductor device. Flipflops in a sequential circuit in a semiconductor device are arranged to be a shift register that can be scanned (a shift register formed of a plurality of flipflops is referred to as a scan chain). In the scan-path testing method, test data is fed to an internal circuit (a combination circuit) by the flipflops while data is shifted through the shift register, and then, the shift register captures data from the internal circuit and shifts and outputs the data. In this way, the test is facilitated.
FIG. 8
shows a portion of a scan test circuit incorporated into a conventional semiconductor device.
A scan test circuit
1
shown in
FIG. 8
includes selectors
12
_
1
through
12
_
4
, and flipflops
10
_
1
through
10
_
4
. Although scan test circuits typically include a number of selectors and flipflops, the scan test circuit
1
here includes four selectors and four flipflops for simplicity of explanation.
FIG. 8
also shows an internal circuit (a combination circuit)
11
which is tested by the scan test circuit
1
.
Each of the flipflops
10
_
1
through
10
_
4
in the scan test circuit
1
has a clock input terminal K, a data input terminal D, and a data output terminal Q.
Each of the selectors
12
_
1
through
12
_
4
in the scan test circuit
1
has two data input terminals “0” and “1”, a data output terminal, and a select terminal that receives a scan enable signal SE to be discussed later.
The terminals “0” of the selectors
12
_
1
and
12
_
2
are connected to the internal circuit (not shown). The terminal “1” of the selector
12
_
1
is connected to an SIN (Serial In) terminal. The terminal “1” of the selector
12
_
2
is connected to the data output terminal Q of the flipflop
10
_
1
.
The terminals “0” of the selectors
12
_
3
and
12
_
4
are connected to the internal circuit
11
. The output terminals of the selectors
12
_
1
through
12
_
4
are respectively connected to the data input terminals D of the flipflops
10
_
1
through
10
_
4
. Each clock input terminal K of the flipflops receives a clock CLK from outside the scan test circuit
1
.
The data output terminals Q of the flipflops
10
_
1
and
10
_
2
are respectively connected to the internal circuit
11
. The data output terminal Q of the flipflop
10
_
1
is also connected to the terminal “1”, of the selector
12
_
2
. The data output terminal of the flipflop
10
_
2
is also connected to the terminal “1” of the selector
12
_
3
. The data output terminal Q of the flipflop
10
_
3
is connected to the terminal “1” of the selector
12
_
4
and the internal circuit (not shown). The data output terminal Q of the flipflop
10
_
4
is connected to an SOUT (Serial Out) terminal discussed later and the internal circuit (not shown).
The scan test circuit
1
is set to be in a shift mode when the SE signal input to the selectors
12
_
1
through
12
_
4
remains at a high level. The scan test circuit
1
is set to be in a capture mode when the SE signal remains at a low level.
FIG. 9
is a timing diagram of the clock CLK and the SE signal input to the scan test circuit
1
shown in FIG.
8
.
FIG. 9
illustrates the SE signal that is transitioned from a high level to a low level, and from a low level to a high level, and clock pulses T
1
through T
5
of the clock CLK in the order of occurrence.
With the SE signal at a high level as illustrated in
FIG. 9
, clock pulses T
1
and T
2
are generated, and with the SE signal at a low level, clock pulse T
3
is generated. With the SE signal returning to a high level, clock pulses T
4
and T
5
are generated.
The procedure of the scan test using the scan test circuit
1
will now be explained. Referring to
FIG. 9
, in a state (the shift mode) during which a high-level SE signal is being input to the selectors
12
_
1
through
12
_
4
in the scan test circuit
1
, test data is sent to the flipflops
10
_
1
through
10
_
4
through the selectors
12
_
1
through
12
_
4
at the timing of the rising edge of each of the clock pulses T
1
and T
2
. The data that is sent to the flipflops
10
_
1
and
10
_
2
is also sent to the internal circuit
11
.
In a state (the capture mode) during which a low-level SE signal is being input to the selectors
12
_
1
through
12
_
4
in the scan test circuit
1
, the flipflops
10
_
3
and
10
_
4
capture the data, which has passed through the internal circuit
11
, at the timing of the rising edge of the clock pulse T
3
shown in FIG.
9
.
In a state during which a high-level SE signal is being input to the selectors
12
_
1
through
12
_
4
again, the data captured by the flipflops
10
_
3
and
10
_
4
from the internal circuit
11
is successively shifted at the timing of the rising edge of each of the clock pulses T
4
and T
5
illustrated in FIG.
9
.
The data shifted out from the flipflop
10
_
4
is sent out through the SOUT (Serial Out) terminal illustrated in FIG.
8
. The data shifted out and the expected data are compared with each other to see if the internal circuit
11
operates normally.
The scan-path testing is thus performed on the internal circuit
11
as an object to be tested.
In step with high-speed operation, fine-line design and multi-layer wiring structure of current semiconductor devices, the probability of occurrence of signal delays due to high resistance arising from contact failure of contact holes (via holes) increases.
There is a pressing need for the scan-path testing in the high-speed operation environment to detect a signal delay failure taking place in an internal circuit.
To perform a scan-path test in a semiconductor device at a high speed in a high-speed operation environment, an expensive high-speed tester is required. This increases test costs.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device and a digital circuit, each including a scan test circuit which can perform a scan-path test at an operational environment higher in speed than the currently available environment while involving less test costs.
It is another object of the present invention to provide a method of testing a semiconductor device and a digital circuit with the semiconductor device and the digital circuit operated at a speed higher than that of a clock input from outside, by using a tester which generates a clock lower than the operational speed of the semiconductor device and the digital circuit.
To achieve the above objects, each of a semiconductor device and a digital circuit in one aspect of the present invention includes a scan chain including a plurality of pairs of a selector and a flipflop arranged in cascade, the scan chain performing a capture mode in which in response to a scan enable signal the flipflop captures data from an internal circuit in synchronization with a predetermined clock and a shift mode in which in response to the scan enable signal, one of the data stored in the flipflop and test data input from outside is shifted to a subsequent flipflop in synchronization with the predetermined clock, a clock generator which generates a clock signal in response to one of the rising edge and the falling edge of the clock pulse of another clock signal input from outside as a trigger, and a clock selector which receives the clock signal input from outside and the clock signal generated by the clock generator, and selects one of the two clock signals in response to the scan enable signal for switching between the shift mode and the capture mode, and then feeds the selected clock signal to the clock input terminal of at least one flipflop forming the scan chain.
Preferably, the clock generator generates a clock having one of the falling edge and the rising edge thereof coinciding with one of the ri
Kawasaki Microelectronics Inc.
Lebentritt Michael S.
Phung Anh
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