Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-05-10
2010-02-02
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S226000
Reexamination Certificate
active
07656718
ABSTRACT:
A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.
REFERENCES:
patent: 6178137 (2001-01-01), Uchihira
patent: 2006/0139051 (2006-06-01), Gallo et al.
patent: 2007/0063730 (2007-03-01), Gallo et al.
patent: 11-045581 (1999-02-01), None
patent: 2001-101864 (2001-04-01), None
patent: 1020030085842 (2003-11-01), None
F. Chau & Associates LLC
Samsung Electronics Co,. Ltd.
Tran Michael T
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