Semiconductor device having multi-gate insulating layers and...

Details Semiconductor device having multi-gate insulating layers and... Semiconductor device having multi-gate insulating layers and...

2002-04-24

2003-11-04

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S287000

Reexamination Certificate

active

06642105

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor device and methods of fabricating the same and, more particularly, to a semiconductor device having multi-gate insulating layers and methods of fabricating the same.
BACKGROUND OF THE INVENTION
Most semiconductor devices such as semiconductor memory devices or semiconductor logic devices use a plurality of MOS transistors in order to increase integration density and reduce power consumption. Generally, an oxide layer having a unique thickness is used as the gate insulating layers of all the MOS transistors in the semiconductor device. However, non-volatile memory devices such as electrically programmable read only memory (EPROM) devices, electrically erasable programmable read only memory (EEPROM) devices or flash memory devices require both low voltage MOS transistors operating in a read mode and high voltage MOS transistors operating in an erase or a program mode. Accordingly, at least two kinds of MOS transistors are formed in the non-volatile memory device.
Voltages applied to the high voltage MOS transistor are higher than those applied to the low voltage MOS transistor. Thus, the high voltage MOS transistor should be designed to be different from the low voltage MOS transistor. For example, the gate insulating layer of the high voltage MOS transistor should be thicker than that of the low voltage MOS transistor in order to achieve reliability at the high voltage. As a result, in such devices, it is required to form at least two kinds of gate insulating layers having different thickness from each other, i.e., multi-gate insulating layers, in order to fabricate the non-volatile memory device.
A method of fabricating a non-volatile memory device is taught in U.S. Pat. No. 5,723,355 entitled “Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory,” by Chang et al., which is hereby incorporated herein by reference. This method includes the step of sequentially forming a tunnel oxide layer of a cell transistor and a polysilicon layer for a floating gate on an entire surface of a semiconductor substrate. The polysilicon layer and the tunnel oxide layer are successively patterned to expose the substrate in a high voltage MOS transistor region and the substrate in a logic MOS transistor region. A gate insulating layer for the high voltage MOS transistor is formed at the surface of the exposed semiconductor substrate. The gate insulating layer in the logic MOS transistor region is selectively removed to expose the substrate in the logic MOS transistor region. A gate insulating layer for the logic MOS transistor is formed at the surface of the exposed substrate in the logic MOS transistor region.
According to the U.S. Pat. No. 5,723,355, the tunnel oxide layer in the cell transistor region can be prevented from being in direct contact with a first photoresist pattern exposing the high voltage transistor region and the logic transistor region. Thus, it is possible to prevent the tunnel oxide layer from being contaminated due to the first photoresist pattern. However, the gate insulating layer formed in the high voltage transistor region is in direct contact with a second photoresist pattern exposing only the logic transistor region. Thus, the gate insulating layer for the high voltage transistor can be contaminated by the second photoresist pattern. As a result, the reliability of the gate insulating layer for the high voltage transistor is degraded.
FIG. 1
is a top plan view showing a portion of typical non-volatile memory device having multi-gate insulating layers. In the drawing, the reference character “a” represents a high voltage transistor region in the peripheral circuit region and the reference character “b” represents a cell array region. The cell array region b may correspond to a low voltage transistor region in the peripheral circuit region.
Referring to
FIG. 1
, a first active region
1
a
and a second active region
1
b
are disposed in the high voltage transistor region a and in the cell array region b, respectively. A first gate pattern GP
1
runs across the first active region
1
a
. A first gate insulating layer is interposed between the first gate pattern GP
1
and the first active region
1
a
. The first gate pattern GP
1
comprises a first gate electrode, a first inter-gate dielectric layer and a first dummy gate electrode, which are sequentially stacked.
Similarly, a second gate pattern GP
2
runs across the second active region
1
b
. The second gate pattern GP
2
comprises a floating gate FG, a second inter-gate dielectric layer and a control gate electrode CG, which are sequentially stacked. A second gate insulating layer, i.e., a tunnel oxide layer, is interposed between the floating gate and the second active region
1
b
. The second gate insulating layer is thinner than the first gate insulating layer. The floating gate FG should be separated from an adjacent floating gate (not shown) and is overlapped with a portion of the control gate electrode CG. Thus, two patterning processes are required in order to form the floating gate FG. Specifically, the floating gate is formed through a first patterning process for exposing an isolation region
3
adjacent to the second active region
1
b
and a second patterning process for defining the control gate electrode CG.
In the event that the cell array region b corresponds to the low voltage transistor region in the peripheral circuit region, the second gate pattern GP
2
comprises a second gate electrode, a second inter-gate dielectric layer and a second dummy gate electrode which are sequentially stacked. At this time, the second gate electrode is completely overlapped with the second dummy gate electrode.
FIGS. 2-8
,
9
A,
9
B,
10
,
11
,
12
A and
12
B are cross sectional views for illustrating a fabrication method of a semiconductor device according to conventional technology. In each drawing, the reference character “a” represents the high voltage transistor region of FIG.
1
and the reference character “b” represents the cell array region of FIG.
1
. Also,
FIGS. 2-8
,
10
and
11
are cross sectional views along the line I—I or the line II—II of FIG.
1
. In addition,
FIGS. 9A and 12A
are cross sectional views along the line I—I of
FIG. 1
, and
FIGS. 9B and 12B
are cross sectional views along the line II—II of FIG.
1
.
Referring to
FIG. 2
, a first gate insulating layer
13
, i.e., a gate insulating layer for a high voltage transistor, is formed on an entire surface of a semiconductor substrate
11
. The first gate insulating layer
13
is formed by thermally oxidizing the semiconductor substrate
11
, for example, a silicon substrate. The first gate insulating layer
13
is formed to a thickness of at least 300 A in order to obtain the endurance to high voltages such as a program voltage and/or an erase voltage of 15 volts to 20 volts.
A fist photoresist pattern
15
covering the high voltage transistor region a is formed. The first gate insulating layer
13
is wet-etched using the first photoresist pattern
15
as a etching mask, thereby exposing the substrate
11
of the cell array region b.
Referring to
FIG. 3
, the first photoresist pattern
15
is removed. A thermal oxidation process is applied to the resultant structure where the first photoresist pattern
15
is removed, to thereby form a second gate insulating layer
17
, e.g., a tunnel oxide layer of cell transistor on the exposed substrate of the cell array region b. The second gate insulating layer
17
is formed to a thin thickness of 100 A or the less. At this time, a surface step difference T exists between the first gate insulating layer
13
and the second gate insulating layer
17
as shown in FIG.
3
. The surface step difference T corresponds to at least a thickness difference between the first and second gate insulating layers
13
and
17
.
A first conductive layer
19
and a chemical mechanical polishing (CMP) stopper layer
21
are sequentially formed on the enti

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