Semiconductor device having load device with trench isolation re

Details Semiconductor device having load device with trench isolation re Semiconductor device having load device with trench isolation re

1998-05-20

2000-10-31

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438210, 438238, 438328, 438330, 438361, 438382, 438430, 257508, H01L 21336

Patent

active

061401889

ABSTRACT:
A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.

REFERENCES:
patent: 5854114 (1998-12-01), Li et al.
patent: 5891771 (1999-04-01), Wu et al.
patent: 5993040 (1999-11-01), Harlan Sur
patent: 6008082 (1999-12-01), Rolfson et al.
Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 584-585, 641, Lattice Press.

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