Semiconductor device having LDD-type source/drain regions...

Details Semiconductor device having LDD-type source/drain regions... Semiconductor device having LDD-type source/drain regions...

2002-04-11

2004-11-16

Zarneke, David A. (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06818489

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-24332, filed on May 4, 2001, the disclosure of which is herein incorporated by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and fabrication methods thereof and, more specifically, to semiconductor devices having LDD-type source/drain regions and fabrication methods thereof.
BACKGROUND OF THE INVENTION
As semiconductor devices become more highly integrated, various techniques for forming LDD-type source/drain regions are widely used in order to improve reliability of MOS transistors. In these techniques, it is required to form a gate spacer on sidewalls of the gate electrodes in order to form the LDD-type source/drain regions. In addition, a self-aligned contact technology has been developed in order to increase the integration density of the semiconductor device. Accordingly, a silicon nitride layer is widely used as a material layer for forming the gate spacer. This is because the gate spacer should have an etching selectivity with respect to an interlayer insulating layer comprising a silicon oxide layer.
FIGS. 1
to
3
are cross-sectional views illustrating a conventional method of fabricating a semiconductor device.
Referring to
FIG. 1
, an isolation layer
2
is formed at a predetermined region of a semiconductor substrate
1
to define an active region. After formation of a gate insulating layer
3
on the active region, a gate electrode layer and a capping layer are sequentially formed on an entire surface of the substrate including the gate insulating layer
3
. The capping layer and the gate electrode layer are successively patterned to form a pair of gate patterns
8
that cross over the gate insulating layer
3
. Incidentally, the gate insulating layer
3
may be over-etched. Thus, the active region can be exposed. Each of the gate patterns
8
comprises a gate electrode
5
and a capping layer pattern
7
, which are sequentially stacked.
Impurity ions are implanted into the active region at a dose of 1×10
12
to 1×10
14
atoms/cm2 using the gate patterns
8
as ion implantation masks, thereby forming relatively low-concentration source/drain regions
9
at the active region. A gate spacer
11
, which is composed of a silicon nitride layer, is then formed on the sidewalls of the gate patterns
8
. Using the gate spacer
11
and the gate patterns
8
as ion implantation masks, impurity ions are implanted into the low concentration source/drain regions
9
at a dose of 1×10
15
to 5×10
15
atoms/cm
2
to form relatively high-concentration source/drain regions
13
. The relatively low-concentration source/drain region
9
and the relatively high-concentration source/drain region
13
constitute an LDD-type source/drain region
15
.
Referring to
FIG. 2
, an etch stop layer
17
is formed on an entire surface of the substrate having the LDD-type source/drain region
15
. The etch stop layer
17
is formed of a silicon nitride layer having an etch selectivity with respect to a silicon oxide layer. Thus, a width W
1
of a region, surrounded by the etch stop layer
17
between the adjacent gate patterns
8
is remarkably reduced as compared to the space between the gate patterns
8
. This is due to the presence of the gate spacer
11
and the etch stop layer
17
. As a result, the aspect ratio of the region, which is surrounded by the etch stop layer
17
, is increased. An interlayer insulating layer
19
is then formed on the entire surface of the substrate including the etch stop layer
17
. At this time, a void
21
might be formed in the interlayer insulating layer
19
between the adjacent gate patterns
8
. This is because the region surrounded by the etch stop layer
17
has a high aspect ratio. Such a void
21
degrades the reliability of the semiconductor device.
Referring to
FIG. 3
, the interlayer insulating layer
19
and the etch stop layer
17
are successively patterned to form a first contact hole
23
a
and a second contact hole
23
b
concurrently. The first contact hole
23
a
exposes the LDD-type source/drain region
15
between the gate patterns
8
and the second contact hole
23
b
exposes the LDD-type source/drain region
15
adjacent the isolation layer
2
. The etch stop layer
17
prevents the isolation layer
2
from being recessed. It is difficult to maximize the surface area of the LDD-type source/drain regions
15
, which are exposed by the first and second contact holes
23
a
and
23
b
, due to the gate spacer
11
. In particular, in the event that mis-alignment occurs during the photolithography process for forming the first and second contact holes
23
a
and
23
b
as shown in
FIG. 3
, the surface area of the LDD-type source/drain region
15
exposed by the first contact hole
23
a
is reduced.
According to the conventional technique as described above, it is difficult to maximize the surface area of the LDD-type source/drain region exposed by the contact hole. This is due to the gate spacer, which is formed of a silicon nitride layer. Accordingly, it is difficult to reduce contact resistance in the semiconductor device. In addition, a void may be formed in the interlayer insulating layer due to the gate spacer. Such a void may lead to reliability degradation of the semiconductor device.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide methods of fabricating a semiconductor device capable of improving the reliability of the semiconductor as well as minimizing the contact resistance in the semiconductor device.
It is another feature of the present invention to provide semiconductor devices having maximized contact area and interlayer insulating layer, without voids.
The invention semiconductor device fabricating method includes forming at least one insulated gate pattern on a semiconductor substrate and forming low-concentration source/drain regions at the semiconductor substrate that is located at both sides of the gate pattern. A first conformal etch-stop layer is formed on an entire surface of the substrate having the low-concentration source/drain regions. A spacer is then formed on the sidewall of the gate pattern. Thus, a portion of the first etch stop layer intervenes between the spacer and the gate pattern. The spacer is formed of an insulating layer having etch selectivity with respect to the first etch stop layer.
Using the gate pattern and the spacer as ion implantation masks, impurity ions are implanted into the low-concentration source/drain regions to form high-concentration source/drain regions having higher concentration than the low-concentration source/drain regions. As a result, the LDD-type source/drain regions, which are composed of the low concentration source/drain regions and the high concentration source/drain regions, are formed at both sides of the gate pattern. The spacer is then selectively removed.
In this way, the aspect ratio of the region, which is surrounded by the first etch stop layer between the adjacent gate patterns, becomes reduced. An interlayer insulating layer is formed on the substrate where the spacer is removed. Accordingly, it is possible to remarkably reduce the probability of a void being formed in the interlayer insulating layer, since the spacer is removed. The interlayer insulating layer and the first etch stop layer are successively patterned to form a contact hole that exposes the LDD-type source/drain region. Accordingly, it is possible to maximize the surface area of the exposed LDD-type source/drain region, since the spacer does not exist any more.
Preferably, a second etch stop layer is formed on the resultant structure where the spacer is removed, prior to formation of the interlayer insulating layer.
The first and second etch stop layers are preferably formed of a material layer having an etch selectivity with respect to the interlayer insulating layer and the spacer. More particularly, the first and second etch stop layers may be formed of a silicon nitride l

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