Semiconductor device having gate with negative slope and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S588000, C257SE21182

Reexamination Certificate

active

06878580

ABSTRACT:
A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

REFERENCES:
patent: 6373112 (2002-04-01), Murthy et al.
patent: 6551941 (2003-04-01), Yang et al.
patent: 6605543 (2003-08-01), Zheng
patent: 20020155566 (2002-10-01), Doris et al.
patent: 2003000485 (2003-01-01), None
IBM Technical Disclosure Bulletin, Jun. 1991, US.

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