Semiconductor device having gate spacer containing...

Details Semiconductor device having gate spacer containing... Semiconductor device having gate spacer containing...

1999-09-15

2002-06-04

Wille, Douglas (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S305000, C438S595000, C438S596000, C257S340000, C257S344000, C257S377000, C257S384000

Reexamination Certificate

active

06399451

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a semiconductor device having a gate spacer containing a conductive layer, and a manufacturing method.
2. Description of the Related Art
As a semiconductor device has been highly integrated, the line width of a gate becomes narrower. As a result, reduced channel length in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a LDD (Lightly Doped Drain) structure deteriorates the characteristics of the MOSFET. Such deterioration typically results from degradation of a saturation current characteristic due to hot electrons.
To overcome this problem, a silicide silicon sidewall source/drain structure has been developed, which is disclosed in an article entitled “A Hot-Carrier Degradation Mechanism and Electrical Characteristics in S
4
D n-MOSFET”, IEEE Transactions on Electron Device, Vol. 44, No. 11, November 1997.
FIG. 1
is a cross-sectional view illustrating a conventional semiconductor device having a gate spacer containing a conductive layer.
Referring to
FIG. 1
, a gate electrode
55
, with a gate insulation layer
53
interposed between a semiconductor substrate
51
and the gate electrode
55
, is formed of polysilicon. Side walls of the gate electrode
55
are covered by a spacer insulation layer
57
, and the spacer insulation layer
57
is covered by a conductive spacer
59
. The conductive spacer
59
is covered by a silicide layer
61
covering the top surface of a source/drain region
65
. An insulation layer
63
is formed on the gate electrode
55
to prevent shorts. between the gate electrode
55
and the conductive spacer
59
and/or the silicide layer
61
. The insulation layer
63
may be formed of a double layer of oxide and nitride. Reference numeral
67
represents a LDD region formed using the spacer insulation layer as an ion implantation mask.
Generally, when a strong electric field is applied to a semiconductor device, hot electrons generated from a semiconductor substrate are trapped within the gate insulation layer
53
and spacer insulation layer
57
being adjacent to the LDD region
67
. The trapped hot electrons reduce mobility of a carrier, thereby deteriorating the characteristics of the semiconductor device, for example, the saturation current. The conductive spacer
59
forms a current path where the hot electrons trapped within the gate insulation layer
53
and spacer insulation layer
57
can escape, thereby preventing degradation of the semiconductor device characteristics. In other words, since the trapped hot electrons escape to the source/drain region
65
or the LDD region
67
through the conductive spacer
59
, the deterioration of the characteristics of the semiconductor device due to hot electrons can be suppressed.
However, a conventional semiconductor device has the following disadvantages.
First, in order to prevent the silicide layer
61
and the conductive spacer
59
from being shorted to the gate electrode
55
, spacer insulation layer
57
must be formed thinly, and yet, must sufficiently cover the gate electrode
55
. These competing requirements are very difficult to implement in a fabrication process.
Second, the insulation layer
63
must be formed to prevent the top surface of the gate electrode
55
from being shorted to the silicide layer
61
and the conductive spacer
59
. However, a silicide layer cannot be formed on the gate electrode
55
in such a structure. The lack of a silicide layer causes an increase in delay time when the semiconductor device operates, thereby lowering the operational speed of the semiconductor device.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a semiconductor device having a gate spacer containing a conductive layer, thereby suppressing the degradation of characteristics of the semiconductor device, avoiding shorts between a gate and source/drain, and forming a silicide layer on a gate electrode.
It is another object of the present invention to provide a method for manufacturing the semiconductor device having a gate spacer containing a conductive layer.
Accordingly, to achieve the first object, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode having a gate insulation layer interposed between the gate electrode and a semiconductor substrate, a source/drain region formed on the semiconductor substrate adjacent the gate electrode, a first spacer insulation layer covering the side walls of the gate electrode, a conductive spacer covering the outer portions of the first spacer insulation layer, a second spacer insulation layer covering the outer portions of the conductive spacer, and silicide layers formed on the gate electrode and the source/drain region.
According to a preferred embodiment of the present invention, the semiconductor substrate is a silicon single crystalline wafer or a silicon on insulator (SOI) type semiconductor substrate. The gate electrode is formed of impurity-doped polysilicon. And the first spacer insulation layer is formed of an oxide layer (SiO
2
) or a complex layer containing the oxide layer. Also, the conductive spacer is formed of impurity-doped polysilicon and the second spacer insulation layer is formed of a nitride layer or a complex layer containing the nitride layer.
The source/drain region further comprises a lightly doped drain (LDD) region extending to a channel area under the gate electrode. The conductive spacer is electrically connected to the source/drain region.
Also, the silicide layer is formed of cobalt silicide (CoSi
x
) or titanium silicide (TiSi
x
).
To achieve the second object, there is provided a method for manufacturing a semiconductor device comprising the steps of forming a gate electrode on a semiconductor substrate where a gate insulation layer is formed, forming a LDD region using the gate electrode as an ion implantation mask, forming a first spacer insulation layer [adjacent] the gate electrode, forming a conductive spacer over at least a portion of the first spacer insulation layer, forming a second spacer insulation layer on the conductive spacer, and forming a silicide layer on the gate electrode and a source/drain region.
Preferably, the gate electrode is formed by depositing a polysilicon layer and patterning the same. The first spacer insulation layer, the conductive spacer and the second spacer insulation layer are formed using anisotropic etching, and the anisotropic etching of the conductive spacer is performed such that the top surface of the gate electrode is partially etched to increase the electrical insulation effect by the first spacer insulation layer.
The conductive spacer is formed using impurity-doped polysilicon. Also, the additional step of forming a source/drain region using the gate electrode having the second insulation spacer as an ion implantation mask is performed, after the step of forming the second spacer insulation layer.
Preferably, the silicide layer is selectively formed by depositing a Co or Ti layer over the entire surface of the semiconductor substrate and performing a rapid temperature annealing (RTA) process thereon.
Here, the RTA process is performed such that the conductive spacer is electrically connected to the source/drain region. Also, the conductive spacer is electrically connected to the source/drain region while the silicide layer on the source/drain region is formed more widely than the silicon exposed to the surface of the semiconductor substrate. Alternatively, the conductive spacer is electrically connected to the source/drain region while impurities from impurity-doped polysilicon forming the conductive spacer is diffused into the LDD region under the gate electrode during the RTA process.
According to the present invention, it is possible to suppress the saturation current characteristic degradation due to hot electrons generated when a strong electric field is applied to a semicondu

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