Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-08
2003-09-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S593000
Reexamination Certificate
active
06620681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a control gate, such as a floating gate in a memory device, and a method of making the same, but more particularly to a self-aligned shallow trench isolation technique that simultaneously forms a gate and an active region thereof.
2. Description of the Related Art
During the manufacture of memory devices, the packing density of cells is primarily determined by the layout of cells within the array and the physical dimensions of the cells themselves. Below the half-micron design rule, scalability is limited by photolithographic resolution attainable during manufacturing and by alignment tolerances of masks used during production. Alignment tolerances are, in turn, limited by mechanical techniques employed to form masks and the techniques used to register these masks between layers. Because alignment errors accumulate during multi-stage fabrication, it is preferable to use as few masks as possible. Fewer masks minimizes the likelihood of misalignment. Accordingly, “self-alignment” processing steps have been developed to produce semiconductor devices.
Isolation structures, e.g., field oxides, between individual cells within the memory cell array consume regions of the chip that are otherwise useful for active circuitry. Thus, in order to increase the packing density of memory cells and active circuits within the substrate, it is desirable to minimize the size of these isolation structures. However, the size of the isolation structure is generally dictated by their process of formation and/or the alignment of this structure.
Typically, an isolation structure is grown at various regions of the chip by a thermal field oxidation process, such as a LOCal Oxidation of Silicon (hereinafter referred to as “LOCOS”). According to the LOCOS method, after a pad oxide layer and a nitride layer are successively formed, the nitride layer is subjected to patterning. Then, the patterned nitride layer is used as a mask to selectively oxidize the silicon substrate to form field oxide regions. However, in considering the LOCOS isolation, the growth of oxide may encroach upon the side plane of the pad oxide layer at a lower portion of the nitride layer serving as the mask during selective oxidation of the silicon substrate, thereby creating what is called a bird's beak at the end portion of the field oxide layer. Due to the bird's beak, the field oxide layer extends into the active region of the memory cell thereby decreasing the width of the active region. This phenomenon is undesirable because it degrades the electrical characteristics of the memory device.
For this reason, a shallow trench isolation (hereinafter referred to as “STI”) structure is attractive in making ultra-high scale semiconductor devices. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide layer is deposited to fill up the trench. Thereafter, the oxide layer is etched via an etch back or a chemical mechanical planarizing (CMP) method so as to form a field oxide layer inside the trench.
The foregoing LOCOS and STI methods commonly include a mask step that defines the regions on the substrate of the isolation structure and a step that forms the field oxide layer within those regions. After forming the isolation structure, steps to form the memory cells are carried out. As such, alignment errors associated with forming the isolation structure and memory cells aggregate to induce mis-alignment, which may result in failure of the device.
When making a floating gate of a non-volatile memory device, for example, one method of reducing misalignment includes forming LOCOS isolation structure using a self-aligned floating gate, such as by the process disclosed in U.S. Pat. No. 6,013,551 (issued to Jong Chen, et al.). According to the methods described therein, a floating gate and active region thereof are simultaneously defined and fabricated using a single mask so that alignment errors do not aggregate.
Non-volatile memory devices are used in flash memory devices and have long-time storage capacity, e.g., almost indefinitely. In recent years, demand for such electrically programmable flash memory devices, EEPROMS for example, has increased. Memory cells of these devices generally have a vertically stacked gate structure comprising a floating gate formed at an upper portion of the silicon substrate. The multi-layer gate structure typically includes one or more tunnel oxide or dielectric layers and a control gate over and/or around the floating gate. In a flash memory cell having this structure, data is stored by transferring electrons to and from the floating gate, which is achieved by applying a controlled voltage to the control gate and substrate. The dielectric functions to maintain the potential on the floating gate.
Even though self-aligned STI processes have an advantage of simultaneously forming floating gates and active regions, there is still a drawback because the aspect ratio of gaps formed in the process is increased, which is likely to form seams or voids within the trench during the gap filling. Also, when using a high density plasma (hereinafter referred to as “HDP”) oxide layer to fill these gaps, the edge portion of a polishing end-point detecting layer underlying the HDP oxide layer becomes eroded during deposition of the HDP oxide layer, which undesirably provides a negative slope at the field oxide region. For this reason, gate residues are generated around the bottom of the sloped portion of the field regions during subsequent gate etching procedures.
The above-described problems can be solved by optimizing the conditions during deposition of the HDP oxide layer to enhance the gap filling capability or by using a method that eliminates the negative slope at the field region by means of a wet etchant.
FIGS. 1A
to
1
E are perspective views of a substrate illustrating in succession a method of manufacturing a conventional flash memory device using a self-aligned STI technique.
Referring to
FIG. 1A
, after forming a gate oxide layer (i.e., tunnel oxide layer)
11
on a silicon substrate
10
, a first polysilicon layer
13
and a nitride layer
15
are successively formed on the gate oxide layer
11
.
Referring to
FIG. 1B
, a photolithography process is performed to pattern the nitride layer
15
, the first polysilicon layer
13
, and the gate oxide layer
11
to form a nitride layer pattern
16
, a first floating gate
14
, and a gate oxide layer pattern
12
. Thereafter, exposed portions of the substrate
10
are etched to a predetermined depth to form trench
18
. That is, the active regions and floating gates are simultaneously defined during the trench forming process using a single mask.
Referring to
FIG. 1C
, exposed portions of the trench
18
are subjected to thermal treatment in ambient oxygen atmosphere for curing the silicon damage caused by high energy ion impact during the trench etching process. By doing so, a trench oxide layer
20
is formed along the inner surface including the bottom plane and sidewall of the trench
18
by the oxidation reaction of the exposed silicon with an oxidant.
During the above oxidizing process, the oxidant encroaches upon the side of the gate oxide layer pattern
12
at the lower portion of the first floating gate
14
to form the bird's beaks at both ends of the gate oxide layer pattern
12
. Because of the bird's beaks, the bottom edge portions of the first floating gate
14
are bent outward while both end portions of the gate oxide layer pattern
12
expand, the lower portions of the sidewalls of the first floating gate
14
have positive slope. Here, the positive slope denotes that the slope allows the sidewall erosion with respect to the etchant. In other words, as shown in the drawing, the intrusion of the oxidant into the portion underlying the nitride layer pattern
16
is blocked by the existence of the nitride layer pattern
16
to provide the negative slope at the upper portion of the sidewall of the first floating ga
Kim Min
Kim Sung-tae
Fourson George
Garcia Joannie Adelle
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
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