Semiconductor device gate structure including a gettering layer

Semiconductor device manufacturing: process – Gettering of substrate – By layers which are coated – contacted – or diffused

Reexamination Certificate

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C438S460000, C438S473000, C257SE21321, C257SE29108

Reexamination Certificate

active

07989321

ABSTRACT:
A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.

REFERENCES:
patent: 5348894 (1994-09-01), Gnade et al.
patent: 6300244 (2001-10-01), Itabashi et al.
patent: 6645857 (2003-11-01), Whitefield et al.
patent: 6797572 (2004-09-01), Jeon et al.
patent: 7052943 (2006-05-01), Yamazaki et al.
patent: 7063893 (2006-06-01), Hoffman
patent: 7067195 (2006-06-01), Hoffman et al.
patent: 7297630 (2007-11-01), Kim
patent: 7306982 (2007-12-01), Yamazaki et al.
patent: 7459379 (2008-12-01), Kokubo et al.
patent: 7611972 (2009-11-01), Govindarajan
patent: 7670641 (2010-03-01), Hoffman et al.
patent: 7683418 (2010-03-01), Park et al.
patent: 7758915 (2010-07-01), Hoffman
patent: 2002/0030283 (2002-03-01), Itabashi et al.
patent: 2002/0197935 (2002-12-01), Mueller et al.
patent: 2003/0151074 (2003-08-01), Zheng et al.
patent: 2003/0183915 (2003-10-01), Scheifers et al.
patent: 2003/0228472 (2003-12-01), Hoffman et al.
patent: 2003/0232468 (2003-12-01), Ohnuma
patent: 2004/0028955 (2004-02-01), Hoffman
patent: 2004/0097055 (2004-05-01), Henley et al.
patent: 2004/0101997 (2004-05-01), Maekawa et al.
patent: 2004/0152240 (2004-08-01), Dangelo
patent: 2005/0032336 (2005-02-01), Yamazaki et al.
patent: 2005/0282341 (2005-12-01), Park et al.
patent: 2006/0189156 (2006-08-01), Doczy et al.
patent: 2006/0193976 (2006-08-01), Hoffman
patent: 2006/0222763 (2006-10-01), Hoffman et al.
patent: 2007/0059910 (2007-03-01), Pei et al.
patent: 2007/0248756 (2007-10-01), Krisko et al.
patent: 2008/0183235 (2008-07-01), Stancer et al.
patent: 2009/0152651 (2009-06-01), Bu et al.
patent: 2009/0267191 (2009-10-01), Minato et al.
patent: 2010/0044806 (2010-02-01), Hou et al.
patent: 1949532 (2007-04-01), None
Changhwan Choi et al., “Aggressively Scaled UltraThin Undoped HfO2 Gate Dielectrode (EOT < 0.7 nm), With TaN Gate Electrode Using Engineered Interface Layer”, IEEE Electron Device Letters, vol. 26, No. 7, Jul. 2005, pp. 454-457.
Chinese Patent Office, Office action mailed Aug. 4, 2010, Application No. 200910141835.8, 6 pages.
Kim, Hyoungsub, et al., “Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer,” Journal of Applied Physics, vol. 96, No. 6, Sep. 15, 2004, 6 pages.

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