Semiconductor device employing buried insulating layer and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S238000, C257S306000, C257SE27084, C257SE27086

Reexamination Certificate

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07321144

ABSTRACT:
A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

REFERENCES:
patent: 5936277 (1999-08-01), Takeuchi
patent: 6407427 (2002-06-01), Oh
patent: 6429091 (2002-08-01), Chen et al.
patent: 6514809 (2003-02-01), Xiang
patent: 2002/0052077 (2002-05-01), Tee et al.
patent: 2002/0097608 (2002-07-01), Skotnicki et al.
patent: 2001-0045580 (2001-06-01), None
English language abstract of Korean Publication No. 2001-0045580.
Tsutomu Sato, et al., “Son (Silicon on Nothing) MOSFET Using ESS ( Empty Space in Silicon) Technique for SoC applications” IEEE 2001, 4 pages.
S. Monfray, et al., “First 80nm SON (Silicon-On-Nothing MOSFETs With Perfect Morphology and High Electrical Performance” IEEE 2001 4 pages.
S. Monfray, et al., “50nm-Gate All Around (GAA)-Silicon On Nothing (SON)-Devices: A Simple Way to Co-Integration of GAA Transistors Within Bulk MOSFET Process” IEEE 2002, 2 pages.
S. Monfray, et al., “SON (Silicon-On-Nothing) P-MOSFETs With Totally Silicided (CoSi2) Polysilicon On The Simplest Way to Integration of Metal Gates on Thin FD Channels”, IEEE 2002, 4 pages.

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