Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-01-27
2002-06-11
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S777000, C257S686000, C257S780000, C438S108000, C438S109000
Reexamination Certificate
active
06404062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates structures and methods for fabricating semiconductor devices, and more particularly to a structure and a method for mounting a flip-chip semiconductor device in which an under-filler is introduced into a space between a semiconductor chip and an wiring layer and a space between the wiring layer and a mounting substrate such as a printed circuit board.
In recent years, with increasing demand for miniaturization, lightweight and thinness of electronic apparatuses, semiconductor devices, which are used therein, have been produced smaller, lighter and thinner. For this reason, semiconductor devices, which are package types such as BGA (Ball Grid Array), CSP (Chip Size Package), MCM (Multi Chip Module) and the like, have been developed.
With regard to internal connecting we processes thereof, a wire bonding process and a flip-chip mounting process are generally employed.
It is predicted, however, that the flip-chip mounting process is becoming the mainstream in terms of its supporting area-pads and multi-bins and of being available to shorten lengths of wires.
It should be noted that, by the flip-chip mounting process, a plurality of protruding electrodes are formed on a surface of a semiconductor chip on which various semiconductor elements are formed and the electrodes are connected to an interconnecting substrate in a face-down state. In such a face-down state, however, since the protruding electrodes directly receive a stress resulting from a difference in thermal expansion coefficients between the semiconductor chip and the interconnecting substrate, there brings about a problem that the protruding electrodes cannot stand such a stress, for example, in a temperature cycling test or the like.
In general, after the flip-chip mounting process is completed, an under-filler is introduced into a space between the semiconductor chip and the interconnecting substrate so as to increase a contact area therebetween and relax the stress applied to the protruding electrodes. Mostly, with respect to flip-chip type semiconductor devices such as BGA, CSP and MCM, during a secondary mounting for mounting them on the printed circuit board, the further under-filler is introduced into the space therebetween so that connecting reliability can be ensured after the secondary mounting.
2. Description of the Related Art
FIG. 1A
shows a conventional semiconductor device
10
A. FIG
1
B shows a state in which the semiconductor device
1
OA is mounted on a motherboard
19
serving as the printed circuit board.
As shown in
FIG. 1A
, the semiconductor device
10
A is a BGA-and-CSP package type semiconductor device, and generally comprises a semiconductor chip
11
, a flexible printed substrate
12
, a plurality of solder balls
13
, and a first under-filler layer
18
.
The semiconductor chip
11
has a circuit-forming surface (a bottom surface thereof in diagrams) on which a plurality of bumps
14
are provided. The bumps
14
are respectively soldered to a plurality of bonding pads
16
of the flexible printed substrate
12
, which serves as an wiring substrate. Thus, the semiconductor chip
11
is mounted on the flexible printed substrate
12
in a face-down state by a flip-chip mounting process (a primary mounting).
Further, on the flexible printed substrate
12
are formed a plurality of connecting holes
17
, positions of which are determined by respective connecting positions of the solder balls
13
to be described later. Moreover, on the flexible printed substrate
12
are formed wiring patterns
15
, each having one end integrally connected to the bonding pad
16
and the other end connected to a connector plug filling the connecting hole
17
.
The solder balls
13
serve as connecting terminals and are soldered to a surface opposite to a chip-carrying surface of the flexible printed substrate
12
. The solder balls
13
are connected to the wiring patterns
15
through the connecting holes
17
, respectively. Accordingly, the semiconductor chip
11
and the solder balls
13
are electrically connected over the flexible printed substrate
12
, which serves as the interconnecting substrate.
Also, the first under-filler layer
18
is formed by introducing the under-filler, which is formed of resin, into a space between the semiconductor chip
11
and the flexible printed substrate
12
. Thus, by forming the first under-filler resin layer
18
in the space therebetween, the bumps
14
can be reinforced. Accordingly, the bumps
14
can be prevented from being detached from the flexible substrate
12
, even though a stress resulting from the difference in thermal expansion coefficient therebetween is applied thereto.
The previously described semiconductor device
10
A, as shown in
FIG. 1B
, is mounted on the motherboard
19
by soldering the solder balls
13
to respective connecting electrodes
21
thereof. This is regarded as a secondary mounting. During the secondary mounting, the under-filler is introduced into a space between the flexible printed substrate
12
and the motherboard
19
so as to form a second under-filler resin layer
20
therewithin. Thus, connection reliability of the solder balls
13
can be improved.
A semiconductor device
10
B shown in
FIG. 2A
, similar to the semiconductor device
10
A shown in
FIG. 1A
, is a face-down semiconductor device belonging to the conventional BGA and CSP types. However, the semiconductor device
10
B is provided with a printed wiring substrate
23
instead, serving as the interconnecting substrate.
The semiconductor chip
11
is, in a face-down state, connected to the printed wiring substrate
23
, upon which a plurality of the bonding pads
16
are formed, whereas under which a plurality of boll pads
22
are formed. The bonding pads
16
and the ball pads
22
are connected through not-shown through-holes.
The bonding pads
16
are connected to the semiconductor chip
11
via the respective bumps
14
. In order to relax the stress applied to these bumps
14
, the under-filler resin is introduced into a space between the semiconductor chip
11
and the printed wiring substrate
23
so as to form the first under-filler layer
18
. Further, the solder balls
13
are respectively soldered to the ball pads
22
which are formed on the lower surface of the printed wiring substrate
23
. Thus, the semiconductor chip
11
and the solder balls
13
are electrically connected by the printed wiring substrate
23
serving as the interconnecting substrate.
By soldering the solder balls
13
to the respective connecting electrodes
21
of the motherboard
19
, the previously described semiconductor device
10
B, as shown in
FIG. 2B
, is mounted thereon. This is regarded as the secondary mounting. During the secondary mounting, the under-filler resin is introduced into a space between the printed wiring substrate
23
and motherboard
19
so as to form the second under-filler resin layer
20
therewithin. Thereby, the connection reliability of the solder balls
13
can be improved.
FIGS. 3 through 6
are diagrams showing a conventional method for producing a semiconductor device and a conventional method for mounting the same. The semiconductor device
10
B, which have been described with reference to
FIG. 2
, is now used as an example in the following description of the conventional methods.
FIG. 3A
is a flowchart showing the method for producing the semiconductor device
10
B. The producing method proceeds as follows.
Firstly, at Step
10
(“Step” simply referred as to “S” in the diagrams), a well-known producing process is performed on a wafer so as to produce a plurality of the semiconductor chips
11
thereon. And then, at Step
11
, a bump-forming process is performed so as to form a plurality of the bumps
14
on the semiconductor chips
11
which have been produced at Step
10
. Thereafter, at Step
12
, a dicing process is performed to dice the wafer so as to individualize the semiconductor chips
11
thereon.
In addition, at Step
13
, a separate pro
Nogami Sachiko
Takashima Akira
Taniguchi Fumihiko
Armstrong Westerman & Hattori, LLP
Clark Sheila V.
Fujitsu Limited
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