Semiconductor device and method of outputting data therein

Details Semiconductor device and method of outputting data therein Semiconductor device and method of outputting data therein

2002-03-19

2003-07-08

Le, Don (Department: 2814)

Electronic digital logic circuitry

Interface

Current driving

C326S093000, C326S026000

Reexamination Certificate

active

06590421

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-14112, filed on Mar. 19, 2001, which is commonly owned and incorporated by reference herein.
BACKGROUND
1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of minimizing skew between plural-bit output data and a method thereof.
2. Description of Related Art
Semiconductor devices that output data comprising a large number of bits typically output the data bits simultaneously (i.e., in parallel). When the logic levels of the plural-bit output data simultaneously transition, a large amount of electrical current is applied to a power line, which causes a transition noise due to parasitic components of the power line. As a result, output data can be delayed and distorted.
Further, if a portion of the output data transits in one direction to a logic state (e.g., from a logic “high” to a logic “low” level), and another portion of the output data transits in the opposite direction (e.g., from a logic “low” to a logic “high” level), a delay time difference occurs between the output data because of the difference of the transition directions. As a result, skew occurs between the output data. The skew will increase as the number of bits comprising the output data increases, the parasitic components increase, and as the operation speed increases.
FIG. 1
is a circuit diagram illustrating a conventional data output circuit. The data output circuit comprises a plurality of data output drivers
10
-
1
to
10
-
n,
parasitic components
12
and
14
, and a capacitor C
3
. The data output drivers
10
-
1
to
10
-
n
drive input data bits D
1
to D
n
to generate output data bits DQ
1
to DQn, respectively. Each of the data output drivers
10
-
1
to
10
-
n
comprises an inverter comprising a PMOS transistor P
1
and an NMOS transistor N
1
. The parasitic component
12
is represented by a resistor R
1
, an inductor L
1
, and a capacitor C
1
, connected between an external power voltage VDDQ and each power voltage terminal of the data output drivers
10
-
1
to
10
-
n.
The parasitic component
14
is represented by a resistor R
2
, an inductor L
2
and a capacitor C
2
, connected between an external ground voltage VSSQ and each ground voltage terminal of the data output drivers
10
-
1
to
10
-
n.
The data output drivers
10
-
1
to
10
-
n
drive the input data bits D
1
to Dn to generate the output data bits DQ
1
to DQn, respectively. When the output data bits DQ
1
to DQn change their logic levels (e.g., from a high level to a low level or vice versa), a large amount of current is drawn through power lines for receiving the external power voltage VDDQ and for receiving the external ground voltage VSSQ. Consequently, a transition noise occurs due to the parasitic components
12
and
14
. The capacitor C
3
is connected between the parasitic components
12
and
14
for interactively changing the external power voltage VDDQ and the external ground voltage.
FIGS. 2A
to
2
C are graphs illustrating a relationship between the external power voltage VDDQ the external ground voltage VSSQ, and the output data bits DQ
1
to DQn of
FIG. 1
, during logic level transitions of output data bits DQ
1
to DQn.
As illustrated in
FIG. 2A
, when input data bits D
1
to D((n+2) transition from a logic “low” level to a logic “high” level and input data bits D((n+1)/2) to Dn transition from a logic “high” level to a logic “low” level, output data bits DQ
1
to DQ(n/2) transition from a logic “high” level to a logic “low” level and output data bits DQ((n+1)/2) to DQn transition from a logic “low” level to a logic “high” level. Because of the transition of each of the n/2 bits, the level of the external power voltage VDDQ falls and a level of the external ground voltage VSSQ rises.
As further illustrated in
FIG. 2B
, when input data bits D
1
to D(n−1) transition from a logic “low” level to a logic “high” level and input data bit Dn transitions from a logic “high” level to a logic “low” level, output data bits DQ
1
to DQ(n−1) transition from a logic “high” level to a logic “low” level and output data bit DQn transitions from a logic “low” level to a logic “high” level.
At this moment, because the input data bits D
1
to D(n−1) transition from a logic “low” level to a logic “high” level, the voltage levels of the external ground voltage VSSQ and the external power voltage VDDQ rise significantly due to the capacitor C
3
. Consequently, a threshold voltage of each NMOS transistor N
1
of the data output drivers
10
-
1
to
10
-
n
rises, causing the transition time from a logic “high” to a logic “low” level of the output data bits DQ
1
to DQ(n−1) to become slower as shown in FIG.
2
B. Further, a threshold voltage of each PMOS transistor P
1
of the data output drivers
10
-
1
to
10
-
n
also rises, so that the transition time from a logic “low” to a logic “high” level of the output data bit DQn becomes faster. That is, skew occurs between output data bits DQ
1
to DQ(n−1) and the output data bit DQn, as illustrated in FIG.
2
B.
Further, as shown in
FIG. 2C
, when the transition time from a logic “low” to a logic “high” level of the output data bits DQ
1
to DQ(n−1) becomes slower, and the transition time from a logic “high” to a logic “low” level of the output data bit DQn becomes faster, skew occurs between the output data bits DQ
1
to DQ(n−1) and the output data bit DQn.
As described above, in conventional semiconductor devices, as the number of output bits increases, skew occurs between output data that transitions from a logic “high” level to a logic “low” level and other output data that transitions from a logic “low” level to a logic “high” level.
SUMMARY OF THE INVENTION
To overcome the above problems, it is an object of the present invention to provide a semiconductor device and output method thereof for minimizing skew between plural-bit output data.
According to one aspect of the present invention, a data output circuit of a semiconductor device comprises a plurality of data output drivers for generating plural-bit output data. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state, in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state, in response to signals received from other data output drivers.
Preferably, the first delay circuit comprises a plurality of first switching devices, which are activated in response to the first state of the input data, for transitioning a level of the input data from the first state to the second state; and a plurality of first capacitors for delaying the transition delay time of the input data having the first state. Each of first capacitors are connected to a corresponding one of the first switching devices and an internal ground voltage. The second delay circuit preferably comprises a plurality of second switching devices, which are activated in response to the second state of the input data, for transitioning a level of the input data from the second state to the first state; and a plurality of second capacitors, connected between the plurality of the second switching devices and an internal ground voltage, for varying the transition delay time of the input data having the second state.
According to another aspect of the present invention, a semiconductor device comprises a controller for receiving plural-bit input data and a plurality of data output drivers. The plural-bit input data comprise a first group of bits that transition from a first state to a second state and a secon

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