Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-31
2004-08-31
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S289000, C257S328000, C257S403000, C257S402000, C257S404000
Reexamination Certificate
active
06784059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, further detailedly relates to technique for integrating various type of MOS transistors composing a driver for driving a liquid crystal for example on one semiconductor substrate.
2. Description of the Related Art
Referring to the drawings, a conventional type semiconductor device and its manufacturing method will be described below. The driver for driving a liquid crystal described above is composed of an N-channel MOS transistor and a P-channel MOS transistor which are respectively a logic device of 3 V for example, an N-channel MOS transistor and a P-channel MOS transistor respectively of 30 V for example which respectively have high resistance to voltage, an N-channel double-diffused (D) MOS transistor and a P-channel DMOS transistor and an N-channel MOS transistor of 30 V for example for a level shifter and others.
As for the DMOS transistor structure described above, impurities different in a conductive type are diffused into a diffused layer formed on the side of the main surface of a semiconductor substrate so as to form a new diffused layer, difference in diffusion in the lateral direction of these diffused layers is utilized for effective channel length and a short channel is formed to be a device in which on-state resistance is reduced.
FIG. 12
is a sectional view for explaining a conventional type MOS transistor and shows the structure of an N-channel DMOS transistor as an example. The description of the structure of a P-channel MOS transistor is omitted, however, it is well-known that a P-channel MOS transistor is different only in a conductive type from an N-channel MOS transistor and has the similar structure.
As shown in
FIG. 12
, a reference numeral
51
denotes a semiconductor substrate of one conductive type, for example a P-type,
52
denotes an N-type well, a P-type body layer
53
is formed in the N-type well
52
, an N-type diffused layer
54
is formed in the P-type body layer
53
and an N-type diffused layer
55
is formed in the N-type well
52
. A gate electrode
57
is formed on the surface of the substrate via a gate oxide film
56
and a channel layer
58
is formed in the superficial area of the P-type body layer
53
immediately under the gate electrode
57
.
The N-type diffused layer
54
functions as a source diffused layer, the N-type diffused layer
55
functions as a drain diffused layer and the N-type well
52
under an oxide film
59
according to LOCOS method functions as a drift layer. Reference numerals
60
and
61
respectively denote a source electrode and a drain electrode,
62
denotes a P-type diffused layer for acquiring the electric potential of the P-type body layer
53
and
63
denotes a layer insulating film.
In the DMOS transistor described above, the concentration on the surface of the N-type well
52
is enhanced by diffusing impurities into it, as a result, current easily flows on the surface of the N-type well
52
and resistance to voltage can be enhanced.
The DMOS transistor having such structure is, called surface relaxation-type ((REduced SURface Field: RESURF) DMOS and the concentration of dopants in the drift layer of the N-type well
52
is set so that it meets a condition of RESURF Such technique is disclosed in JP-A-9-139438 and others.
In the DMOS transistor described above is formed, high temperature heat treatment for forming the P-type body layer
53
is required after a gate electrode is formed, therefore, as the concentration in a profile ruled every 0.35 &mgr;m for example in a microdevice operated at low voltage gets out of order, a micro MOS transistor starts to be formed in the present circumstances after a gate electrode of a DMOS transistor is formed and high temperature heat treatment for forming a P-type body layer is finished and there is a problem that a manufacturing process is extended.
As the gate length of the DMOS transistor is basically determined by diffusion coefficients by different ions and a diffusion started position, there is also a problem that the degree of the freedom in design of gate length is small.
SUMMARY OF THE INVENTION
The invention is made to solve the problems and a semiconductor device according to the invention is characterized in that, a gate electrode formed on a P-type well via gate oxide film, a high concentration N-type source layer and a high-concentration N-type drain layer respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer and respectively parted by a P-type body layer formed under the gate electrode are provided.
Also, the semiconductor device according to the invention is characterized in that, a gate electrode formed on a first conductive type well via a gate oxide film, a high-concentration N-type source layer formed so that it is adjacent to one end of the gate electrode, a high-concentration second conductive type drain layer formed apart from the other end of the gate electrode, a low-concentration first conductive type drain layer extended from under the gate electrode and formed so that the low-concentration second conductive type drain layer surrounds the second conductive type drain layer and a second conductive type body layer formed between the second conductive type source layer under the gate electrode and the second conductive type drain layer are provided.
Preferably the step of forming the second conductive type body layer is formed by ion implantation.
According to the above feature, although channel length is determined as a one value in the convenient thermal procedure, since channel length can be determined more freely with respect to gate length according to designing the body layer, in comparison with the conventional method.
Further since the body layer of the present invention is formed only below the gate electrode, junction capacity can be reduced in comparison with the conventional body layer formed so as to cover the high concentration source layer.
Furthermore, high temperature thermal procedure for forming the body layer after forming the gate electrode is not required, hybrid integration with very small sized process can be realized.
Further, preferably p type layer for controlling a threshold voltage is formed on a surface portion (channel region) of the N type body layer is formed.
According to the above feature, a driving ability of p channel DMOS transistor normally being inferior to n channel MOS transistor can be improved.
According to the present invention, by forming impurity layer of each conduction type in each of the channel layers corresponding to the conduction type of the body layers, the driving capability of reverse conduction type of transistors formed on a substrate can be made uniform.
In the same conduction type of transistors which are different size, by forming impurity layer of conduction type in the channel layers of the body layers, the driving capability can be controlled.
REFERENCES:
patent: 4062699 (1977-12-01), Armstrong
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5567629 (1996-10-01), Kubo
patent: 5688700 (1997-11-01), Kao et al.
patent: 5814858 (1998-09-01), Williams
patent: 5844272 (1998-12-01), Soderbarg et al.
patent: 5926712 (1999-07-01), Chen et al.
patent: 6033944 (2000-03-01), Shida
Aoyama Masashige
Arai Takashi
Taniguchi Toshimitsu
Yoshitake Kazuhiro
Admoso Samuel
Loke Steven
Sanyo Electric Co,. Ltd.
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