Semiconductor device and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S217000, C438S276000, C438S290000

Reexamination Certificate

active

06403422

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, and more specifically to the improvements in the pattern configuration of an ROM region of a semiconductor device incorporating an ROM (Read Only Memory) and to a method of manufacturing the device.
2. Description of the Background Art
In general, in manufacturing a semiconductor device incorporating an ROM formed using photolithography and ion-implantation techniques, the specifications of the ROM vary according to the needs of the customers. Consequently, since all semiconductor devices employ masks of identical specifications, during the manufacturing steps of the semiconductor device incorporating an ROM, the same manufacturing steps are adopted as far as the step preceding the forming step of an ROM region. As a result, the structures of the semiconductor devices at this unfinished stage are identical, and in this unfinished condition the semiconductor devices are stored for the time being.
Then, after the specifications of an ROM are determined based on the order placed by the customer, the manufacturing steps for the unfinished semiconductor device are resumed, an ROM region is patterned according to the ROM specifications, and the final manufacturing steps are carried out.
Referring now to
FIG. 14
, the planar pattern structure of an ROM region in the conventional semiconductor device will be described.
Element isolating regions
12
are disposed regularly at predetermined intervals in the X and Y directions, and gate interconnection layers
13
extending in the Y direction are disposed at predetermined intervals in the X direction.
Aluminum interconnection layers
10
extending in the X direction are disposed at predetermined intervals in the Y direction in regions between element isolating regions
12
. A plurality of contact holes
9
are provided in aluminum interconnection layer
10
to provide electrical connection to active regions on a semiconductor substrate
1
. A channel region
14
of an ROM transistor is formed on semiconductor substrate
1
where gate interconnection layer
13
and aluminum interconnection layer
10
intersect.
Referring now to
FIGS. 15-19
, the manufacturing steps of an ROM transistor formed in the ROM region having the above-mentioned structure will be described below.
Referring first to
FIG. 15
, element isolating region
12
as shown in
FIG. 14
is formed in a matrix using the LOCOS (Local Oxidation of Silicon) method to define an active region in a given region on the surface of silicon semiconductor substrate
1
.
Next, a silicon oxide film
2
having a thickness of 100 Å to 300 Å is formed by thermal oxidation on the surface of silicon semiconductor substrate
1
. Thereafter, a polycrystalline silicon layer
3
having a film thickness of 1000 Å to 3000 Å is formed on oxide film
2
using the CVD (Chemical Vapor Deposition) method. Then, on polycrystalline silicon layer
3
, a tungsten silicide layer
4
having a film thickness of 1000 Å to 3000 Å is formed by sputtering.
Thereafter, silicon oxide film
2
, polycrystalline silicon layer
3
, and tungsten silicide layer
4
are patterned using photolithography and etching techniques. Thus, gate interconnection layer
13
including oxide film
2
, polycrystalline silicon layer
3
, and tungsten silicide layer
4
is completed.
Next, referring to
FIG. 16
, using as a mask the gate interconnection layer
13
including oxide film
2
, polycrystalline silicon layer
3
, and tungsten silicide layer
4
, an n-type impurity such as As is implanted with a dosage of 1×10
15
/cm
2
to 1×10
16
/cm
2
at an implantation energy of 30 keV to 60 keV into semiconductor substrate
1
. Then, the impurity implanted into semiconductor substrate
1
is diffused thermally, and n+ type impurity diffusion regions
5
which later become source/drain regions of an ROM transistor is completed.
Referring now to
FIG. 17
, a resist film
7
of a predetermined pattern is formed selectively on n+ type impurity diffusion region
5
. Thereafter, in order to determine the threshold voltage (Vth) of the ROM transistor, p-type impurity ions
8
such as boron are implanted into channel region
14
at an acceleration voltage, for example at approximately 200 keV, which penetrates oxide film
2
, polycrystalline silicon layer
3
, and tungsten silicide layer
4
to form channel implant
38
.
Referring now to
FIG. 18
, resist film
7
is removed, and then, semiconductor substrate
1
is heat-treated to activate p-type impurity ions
8
. Thereafter, an interlayer insulating film
6
having a thickness of 0.4 &mgr;m to 1.2 &mgr;m and being formed of TEOS (Tetra Ethyl Ortho Silicate) and/or BPSG (Boro Phospho Silicate Glass) is formed by the CVD method so as to cover tungsten silicide layer
4
and n+ type impurity diffusion region
5
. Then, contact hole
9
reaching n+ type impurity diffusion region
5
is formed selectively in interlayer insulating film
6
by etching.
Referring now to
FIG. 19
, aluminum interconnection layer
10
having a film thickness of 0.6 &mgr;m to 1.0 &mgr;m is formed by sputtering, and thereafter, a surface protection film
11
such as a nitride film having a film thickness of 0.5&mgr;m to 1.0 &mgr;m is formed by the CVD method. From the above-described steps, the ROM transistor is formed with its threshold voltage (Vth) set at a predetermined level.
The patterned structure of the aforementioned conventional ROM transistor, however, is as shown in
FIG. 14
in which aluminum interconnection layer
10
crosses channel region
14
where impurity ions are implanted to determine the threshold voltage (Vth) of the ROM transistor.
Thus, the manufacturing steps are interrupted after forming n+ type impurity diffusion regions
5
which later become the source/drain regions of the ROM transistor shown in
FIG. 16
, and the final manufacturing steps shown in
FIGS. 17-19
are performed after the ROM specifications are determined based on the order placed by the customer.
As a result, due to the long manufacturing period required for the final manufacturing steps shown in
FIGS. 17-19
after the ROM specifications are determined, it has been a problem that too much time was required from the time of order to the time when the products are supplied to the customer.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method of manufacturing the device which shortens the manufacturing period required for the final manufacturing steps of a semiconductor device after the ROM specifications are determined.
A semiconductor device according to the present invention is provided with an element isolating region disposed in a matrix for defining an active region on a semiconductor substrate, first conductive layers extending in a direction and disposed at predetermined intervals from each other above the element isolating region, and second conductive layers extending in a direction intersecting the first conductive layers and disposed at predetermined intervals from each other above the first conductive layers. The second conductive layer, also, is disposed above the element isolating region.
Moreover, preferably in the above-mentioned semiconductor device, the active region forms source/drain regions and a channel region, the first conductive layer forms a gate interconnection layer, the second conductive layer forms an aluminum interconnection layer, and the source/drain regions, the channel region, the gate interconnection layer, and the aluminum interconnection layer together form an ROM transistor.
In accordance with one aspect of the method of manufacturing a semiconductor device according to the present invention, the method includes the steps of forming an element isolating region in a matrix to define an active region on a semiconductor substrate, forming a first conductive layer at a given location of the active region defined by t

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