Semiconductor device and method of fabricating same

Details Semiconductor device and method of fabricating same Semiconductor device and method of fabricating same

2001-12-20

2003-04-08

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S631000, C438S637000

Reexamination Certificate

active

06544884

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of fabrication thereof, and the invention relates more particularly to a semiconductor integrated circuit device having multilevel metallization and a method of fabricating such a device.
The structure of a known semiconductor device is shown in FIG.
2
. As can be seen from this figure, in the known semiconductor device, an isolation film
10
, a gate oxide film
11
and gate electrodes
3
are formed on the silicon substrate
2
. A lower metallization layer
5
is formed over the laminate via an interlayer dielectric film
4
. An upper metallization layer
7
is formed over the lower metallization layer
5
via an interlayer dielectric film
6
. The upper metallization layer
7
and the lower metallization layer
5
are electrically connected by electrodes
9
buried in contact holes
8
. This semiconductor device is fabricated in a manner described below.
To electrically isolate individual transistors, the silicon substrate is first thermally oxidized locally to form the isolation film
10
. Then, the gate oxide film
11
is formed by thermal oxidation in regions where transistors should be formed. The gate electrodes
3
are formed on the gate oxide film by a CVD process step and then by a photolithography step. Ions are implanted into the silicon substrate
2
to form a pn junction. Thus, an ion-implanted layer is formed. Thereafter, the interlayer dielectric film
4
is formed over the gate electrodes
3
by CVD. To make the surface of the interlayer dielectric film
4
as flat as possible, the interlayer dielectric film
4
is caused to reflow by annealing, or the interlayer dielectric film is deposited as a thick layer and is etched back.
The lower metallization layer
5
is formed on top of the interlayer dielectric film
4
by sputtering and then by photolithography. The interlayer dielectric film
6
and the upper metallization layer
7
are formed on the lower metallization layer
5
similar, to the lower metallization layer
5
. The contact holes
8
are formed by local etching to electrically connect the upper metallization layer
7
and the lower metallization layer
5
. The buried electrodes
9
are formed inside the contact holes
8
. These techniques are described, for example, in Japanese Patent Laid-Open No. 291763/1992.
Semiconductor devices tend to be packaged with an increasingly larger device density year after year. Concomitantly, it is necessary to increase the depth of the contact holes
8
. In particular, if the semiconductor device
1
has a minimum linewidth of less than 0.5 &mgr;m, a delay in the conductor lines is a rate limiter which impedes improvement of the operating speed of the semiconductor device
1
. To prevent this, the capacitance between the two metallization layers is reduced. For this purpose, the thickness of the interlayer dielectric film is increased. That is, it is necessary to increase the depth of the contact holes
8
. With this trend, it is necessary to increase the depth of the contact holes
8
in devices having minimum linewidths of less than 0.5 &mgr;m, typified by a 256-megabit DRAM, to accomplish higher speeds.
Where more or higher functions are to be imparted to the semiconductor device, the contact holes
8
need to be deeper, which is also the case where higher operating speeds are necessary. For example, an existing computer has been fabricated by mounting both a semiconductor chip having a single function such as a CPU and semiconductor chips acting as memories on a printed-circuit board. In recent years, however, attempts have been made to obtain improved efficiencies or more functions by fabricating a CPU and memories on one chip. This has demanded that the depth of the contact holes
8
be increased. As an example, a combination of a dynamic memory and a logic circuit such as a CPU will be considered. Tall capacitors exist on top of gate electrodes of a dynamic memory. Therefore, the metal interconnection lines are at a higher level than in the logic circuit. The logic circuit needs more metallization layers than memories and so the top metallization layer of the logic circuit must pass over the capacitors. Therefore, the contact holes
8
permitting either connection of these different metallization layers or connection of the top metallization layer and the semiconductor substrate need to be deeper than conventional.
Using a known technique, if the interlayer dielectric film is made thicker, the irregularities on the surface increase. Furthermore, when a metallization layer is patterned photolithographically, defocusing takes place. For these and other reasons, limitations are imposed on the depth of the contact holes
8
.
In recent years, chemical-mechanical polishing (CMP) has permitted perfect planarization. Consequently, no limitations are placed on steps that can be planarized. Hence, application of contact holes
8
which are so deep that they have not been heretofore employed from a point of view of manufacturing yield are now being discussed.
It is considered that this technique is advantageous where a dynamic memory and a logic circuit such as a CPU are both mounted on one chip. In particular, the dynamic memory has tall capacitors on top of gate electrodes and so metallization layers exist at higher positions than the logic circuit. Therefore, in order to connect the memory and the logic circuit within one chip, it is necessary to perform a planarization step so that the interlayer dielectric films
4
and
6
in the logic circuit are thick and that the interlayer dielectric films
4
and
6
in the memory are thin. To planarize steps that are unprecedentedly large, adoption of chemical-mechanical polishing (CMP) is being discussed.
Chemical-mechanical polishing (CMP) is designed to mechanically polish interlayer dielectric films to flatten them. Therefore, it is possible to obtain interlayer dielectric films
4
and
6
having surfaces parallel to the surface of the silicon substrate surface without the sagging experienced in the known etching technique. Especially, in a multifunctional semiconductor device in which a CPU is combined with memories, deep contact holes formed by CMP are considered unavoidable.
However, our research has revealed that simply deepening the contact holes
8
to seek higher functions or higher operating speeds does not result in fabrication of the semiconductor
1
with high reliability. Specifically, if the contact holes
8
are simply deepened without taking account the dimensions at various locations, the electrodes
9
buried in the contact holes
8
peel at the locations of the contact holes
8
at which stress is concentrated. Consequently, electrical connections with a high degree of probability are not feasible.
Furthermore, we have discovered that planarization achieved by CMP increases the possibility of delamination of the buried electrodes. In particular, CMP completely flattens the whole surface of the semiconductor device chip. This increases the stress. In the known technique, different layers are slightly uneven as shown in FIG.
2
and so the stress is distributed (
FIG. 4
a
). The stress concentrated in the corners of the contact holes
8
is mitigated. However, CMP achieves complete planarization, resulting in concentration of the stress in the corners of the contact holes
8
. Hence, delamination is likely to occur.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a reliable semiconductor device which operates at a high speed or has many functions and in which delamination of buried electrodes is prevented.
We have made an intensive investigation to achieve the above-described object and have discovered the mechanism for delamination of a buried electrode. This mechanism is described below with reference to
FIGS. 3-8
.
The buried electrodes delaminate during the processing step for forming a film for creating the buried electrodes
9
shown in FIG.
3
. Thermal stress acting on the buried electrodes is conce

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