Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-23
2006-05-23
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S478000, C438S151000
Reexamination Certificate
active
07049198
ABSTRACT:
An S1-yGeylayer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGeylayers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGeylayer can be suppressed. As a result, the Si/Si1-yGeyinterface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.
REFERENCES:
patent: 5323031 (1994-06-01), Shoji et al.
patent: 5324690 (1994-06-01), Gelatos et al.
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565690 (1996-10-01), Theodore et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5708281 (1998-01-01), Morishita
patent: 5792679 (1998-08-01), Nakato
patent: 5869851 (1999-02-01), Sugawa
patent: 5891769 (1999-04-01), Liaw et al.
patent: 5920088 (1999-07-01), Augusto
patent: 5977560 (1999-11-01), Banerjee et al.
patent: 6049098 (2000-04-01), Sato
patent: 6059895 (2000-05-01), Chu et al.
patent: 6087679 (2000-07-01), Yamazaki et al.
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6143593 (2000-11-01), Augusto
patent: 6190975 (2001-02-01), Kubo et al.
patent: 6350993 (2002-02-01), Chu et al.
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6399993 (2002-06-01), Ohnishi et al.
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6403976 (2002-06-01), Saitoh et al.
patent: 6455364 (2002-09-01), Asai et al.
patent: 6455871 (2002-09-01), Shim et al.
patent: 6472685 (2002-10-01), Takagi
patent: 6492711 (2002-12-01), Takagi et al.
patent: 6537369 (2003-03-01), Saitoh et al.
patent: 6563146 (2003-05-01), Yuki et al.
patent: 6593625 (2003-07-01), Christiansen et al.
patent: 6597016 (2003-07-01), Yuki et al.
patent: 6660393 (2003-12-01), Saitoh et al.
patent: 6667489 (2003-12-01), Suzumura et al.
patent: 6674100 (2004-01-01), Kubo et al.
patent: 6674150 (2004-01-01), Takagi et al.
patent: 0 683 522 (1995-11-01), None
patent: 03003366 (1991-01-01), None
patent: 04-247664 (1992-09-01), None
patent: 07-321222 (1995-12-01), None
patent: 10-093076 (1998-04-01), None
patent: 10-214906 (1998-08-01), None
patent: 2000294699 (2000-10-01), None
F.K. LeGoues et al., “The Mechanisms of Relaxation in Strained Layer GeSi/Si Superlattices: Diffusion vs. Dislocation Formation”, Mat. Res. Soc. Symp. Proc., vol. 103, pp. 185-190, 1998.
M.A. Armstrong et al., “Design of Si/SiGe Heterojunction Complementary Metal-Oside-Semiconductor Transistors”, IEEE IEDM 95, pp. 761-764, 1995.
G.L. Patton et al., “Oxidation of Strained SI-GE Layers Grown by MBE”, Mat. Res. Soc. Symp. Proc., vol. 102, pp. 295-299, 1988.
European Patent Office, Search Report, Aug. 7, 2000, 4 pages.
Osten et al., “Carbon-containing group IV heterostructures of Si: Properties and Device Applications”, 1998, pp. 11-14, Thin Solid Films, XP 000667859.
Lanzerotti et al., “Suppression of Boron Outdiffusion in SiGe HBTs by Carbon Incorporation”, 1996, pp. 249-252, IEEE 10.2.1 IEDM 96.
Croke et al., “Stabilizing the Surface of Morphology of Sil-x-yGexCy/Si Heterostructures Grown by Molecular Beam Epitaxy Through the Use of a Silicon-carbide Source”, Jul./Aug. 1998, pp. 1937-1942, J. Vac. Sci. Technol. B 16(4).
Nesting et al., “The Application of Novel Chemical Precursors for the Preparation of Si-Ge-C Heterostructures and Superlattices”, 1998, pp. 281-286, Mat. Res. Soc. Symp. Proc. vol. 533, Materials Research Society.
Perez-Rodriguez et al., “Ion Beam Synthesis and Recrystallization of Amorphous GiGe-SiC Structures”, 1996, pp. 151-155, Nuclear Instruments and Methods in Physics Research B 120, NIM B Beam Interactions with Materials & Atoms.
Notice of Reasons of Rejection Dated Dec. 16, 2003.
Asai Akira
Katayama Koji
Kubo Minoru
Ohnaka Kiyoshi
Saitoh Tohru
NixonPeabody,LLP
Schillinger Laura M.
Studebaker Donald R.
LandOfFree
Semiconductor device and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3616000