Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2001-12-20
2003-04-22
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S723000, C257S777000
Reexamination Certificate
active
06552419
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to package structure of a semiconductor device using a tape to mount a semiconductor chip, and a liquid crystal module using the semiconductor device.
BACKGROUND OF THE INVENTION
TAB (Tape Automated Bonding), which is a technique to mount a semiconductor chip on a tape made of an organic base material, is used for a liquid crystal display unit employed as a monitor of a personal computer, mobile devices such as a mobile phone and a pocket game machine, and so forth. These devices are mounted using package structures such as a TCP (Tape Carrier Package) and a COF (Chip on Film). The TCP structure is preferable to use in package devices that are of thin designs, and such structures have been widely used in the aforementioned devices.
FIG. 12
is a cross-sectional view describing a typical mounting method using the TCP structure, which has been conventionally known. A tape (tape carrier)
3
is formed by creating a copper wiring pattern
2
on a base
1
made of organic materials such as polyimide. Extending parts
2
a
and
2
b
of the copper wiring pattern
2
extend from the periphery of the base
1
so as to be in parallel with each other. The extending part
2
a
is connected to, for instance, a pad of a liquid crystal panel, whereas the extending part
2
b
is connected to, for instance, a power source and a pad of a printed board to which an image data signal is transmitted. The parts are electrically connected via an anisotropic conductive film, for example.
A device hole
5
is formed in the base
1
corresponding to a semiconductor chip
4
to be mounted. The copper wiring pattern
2
juts into the device hole
5
to form inner leads
2
c
. The inner lead
2
c
and the extending parts
2
a
and
2
b
of the copper wiring pattern
2
are plated with tin (not illustrated). So as to be connected with the gold bumps
6
provided in all four sides of the rectangle semiconductor chip
4
, the inner leads
2
c
juts into the device hole
5
from the four directions.
In the semiconductor chip
4
manufactured by dicing a wafer, i.e., eutectic, the gold bump
6
thereof is bonded with the tin which electroless-plates the inner lead
2
c
, and this arrangement is termed ILB (Inner Lead Bonding).
An element surface of the mounted semiconductor chip
4
and surroundings of the inner lead
2
c
are sealed by potting a resin
7
, so that mechanical strength of the device is retained and the same is protected from the environment. Incidentally, other parts of the tape
3
other than the electrode parts, such as the inner lead
2
c
, are protected with a coating having a solder resist
8
. The processes noted above are successively done on the tape
3
so that the mounting operation is efficiently done.
In the meantime, rapid development of electronic devices in recent years has demanded an arrangement of multiple chips instead of one chip being mounted on one tape. As an example of this, a liquid crystal module, mounted on small devices such as the aforementioned mobile phone and pocket game machine, will be described.
To keep up with an increase in the number of wires in the liquid crystal panel, the liquid crystal module has been arranged so that a memory is provided in a driver IC to boost efficiency of driver operation. However, as a result, memory capacity has been increased due to further growth of the number of pixel and employment of a color display. For instance, an SRAM occupies 60% of the surface of a semiconductor chip when the SRAM is manufactured along with common and segment drivers in a process necessary to manufacture the common and segment drivers.
Meanwhile, a driver part is required to withstand high voltage in order to control pixel contrast of a liquid crystal panel and hence a fine process is unsuitable for manufacturing the driver part. However, the fine process can be applied to manufacturing of a memory part since the same does not necessarily withstand high voltage. That is, although inapplicable to the driver part, the fine process can be applied to a memory part since the same is not under the constraint of voltage, and thus the liquid crystal module can meet the required level of integration in accordance with the number of wires of the liquid crystal panel.
Accordingly, it has been researched to form the driver part and the memory part separately in each optimized process, and then mount the manufactured two semiconductor chips, i.e. a driver chip and a SRAM chip, on one tape.
As a conventional technique to mount two semiconductor chips, for instance, Japanese Laid-Open Patent Publication No. 11-54695/1999 (Tokukaihei 11-54695; published on Feb. 26, 1999) discloses an arrangement as below.
In this arrangement, although not using the ILB process, a second semiconductor chip is stacked on a first semiconductor chip bonded on a lead frame. When stacked, the second semiconductor chip is provided with its face down and a melting point of a solder ball of the upper second semiconductor chip is arranged to be higher than that of a solder ball of the lower first semiconductor chip, so as to prevent the solder ball from dropping when soldering. On this account, the stacking can be fulfilled without using wire-bonding and the height of the package can be held low. Also, the Publication 11-54695/1999 discloses an arrangement wherein the lead frame is omitted by forming the second semiconductor chip to be smaller than the first chip and supporting the unoverlapped part with a supporting lead, so as to lower the chip by the same height.
However, it should be pointed out that the conventional technique as noted above cannot reduce a terminal pitch smaller than 100 &mgr;m due to the use of the solder joint, and hence the arrangement cannot meet the requirement to produce a finer liquid crystal panel.
SUMMARY OF THE INVENTION
The present invention aims at providing a semiconductor device in which a terminal pitch can be shortened and a liquid crystal module using the same, wherein the semiconductor device is arranged so that multiple numbers of chips are stacked.
To achieve the aim above, the semiconductor device of the present invention includes:
a tape carrier including: a wiring pattern formed on an organic base having an opening portion; and the wiring portion including an inner lead portion jutting into the opening portion;
a semiconductor chip mounted in the opening portion of the tape carrier and a first electrode formed on a surface of the semiconductor chip, the first electrode connected to the inner lead via a first gold bump; and
an electronic component, mounted on the tape carrier by stacking onto the semiconductor chip, and the semiconductor chip including a second electrode formed on the same surface as the first electrode, the second electrode connected via a second gold bump to a third electrode formed on a first surface of the electronic component.
According to this arrangement, the semiconductor chip and the inner lead and also the semiconductor chip and the electronic component are connected via the gold bumps, when the semiconductor device using TCP structure is arranged so that multiple numbers of chips are stacked, namely the semiconductor chip is mounted by ILB and another electronic component is further mounted thereon.
In this manner, the gold bump is less deformed when connected to the electrodes than soft solder bumps which is softer than the gold bump. Furthermore, the terminal pitch can be shortened to, for instance, around 45 &mgr;m so that not less than 450 terminals can be provided on a chip which is around 20 mm long. As a result, the arrangement can meet the requirement to produce a finer liquid crystal panel.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4763188 (1988-08-01), Johnson
patent: 5471369 (1995-11-01), Honda et al.
patent: 5646829 (1997-07-01), Sota
patent: 5724233 (1998-03-01), Honda et al.
patent: 5917242 (19
Cruz Lourdes
Sharp Kabushiki Kaisha
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