Semiconductor device and fabrication method thereof

Details Semiconductor device and fabrication method thereof Semiconductor device and fabrication method thereof

1998-11-06

2002-08-20

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S239000, C438S393000

Reexamination Certificate

active

06436756

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The present invention claims priority from Japanese Patent Application No.9-288467 filed Oct. 21, 1997, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a gallium-arsenide integrated circuit for use in a micro wave circuit and, particularly, to a technique for integrating a large capacitor formed of high dielectric constant material and a small capacitor formed of a dielectric material having relatively low dielectric constant.
2. Description of Related Art
In a gallium-arsenide (GaAs) integrated circuit for use in a micro wave circuit, a field effect transistor (FET), a large capacitor used for a power source or used as a coupling capacitor and a small capacitor necessary in matching circuits have been integrated. As a dielectric material between electrodes of a large capacitor, a thin film of SrTiO
3
(STO), BaTiO
3
, [Ba
x
Sr
1−x
]TiO
3
(BST), PbTiO
3
or [PbZr]TiO
3
(PZT), etc., whose relative dielectric constant is 100 or more is used. SiN
x
having relative dielectric constant as low as about 7 is used as a dielectric material between electrodes of a small capacitor.
Japanese Patent Application Laid-open No. Hei 6-120425 discloses an integration of FET and capacitors. According to the disclosed technique, the FET is formed first and, then, the large capacitor is formed by using high dielectric constant material.
However, since, in the disclosed technique, the FET and the capacitor are formed separately, the number of manufacturing steps is increased. Further, in order to form the capacitor having different capacity, other manufacturing steps are required.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which is an integrated circuit including capacitors having substantially different capacitances and a manufacturing method for manufacturing the semiconductor device with a smaller number of manufacturing steps.
According to a first aspect of the present invention, an upper electrode of a capacitor having small capacitance (referred to as “small capacitor”, hereinafter) and a lower electrode of a capacitor having large capacitance (referred to as “large capacitor”, hereinafter) are formed simultaneously. That is, after a film of low dielectric constant material is formed on a lower electrode of the small capacitor, the upper electrode of the small capacitor and the lower electrode of the large capacitor are formed simultaneously and a film of high dielectric constant material and the upper electrode are laminated on the lower electrode of the large capacitor. Thus, a semiconductor device in which the upper electrode of the small capacitor and the lower electrode of the large capacitor are formed as different regions of the same conductive film. It is enough that dielectric constant of the film of low dielectric constant material is lower than dielectric constant of the film of high dielectric constant material formed on the lower electrode of the large capacitor. The conductive film may be of a metal material or a conductive oxide material.
It is preferable to form an active elements on a substrate and form the lower electrode of the small capacitor simultaneously with the formation of electrodes of the active element.
In detail, at the time of formation of the electrode, for example, a gate electrode of the active element, the metal film is left on a portion of the substrate. The active element and the metal film are covered by an inter-layer film. An opening is formed in the inter-layer film such that a portion of the metal film is exposed. On the wafer, a dielectric film of a dielectric material having low dielectric constant (referred to as “low dielectric constant film”, hereinafter), a first conductive film, a dielectric film of a dielectric material having high dielectric constant (referred to as “high dielectric constant film”, hereinafter) and a second conductive film are formed in the order. The large capacitor is formed by processing the second conductive film, the high dielectric constant film and the first conductive film and the small capacitor is formed by removing the second conductive film and the high dielectric constant film correspondingly to the position of the metal film and processing the first conductive film.
According to a second aspect of the present invention, the dielectric material between the electrodes of the small capacitor has a double layer structure composed of a high dielectric constant film and a low dielectric constant film, the low dielectric constant film of the large capacitor is removed and the lower electrodes of the small and large capacitors are formed simultaneously and the upper electrodes of the small and large capacitor are formed simultaneously. That is, the lower electrode of the small capacitor and the lower electrode of the large capacitor are formed simultaneously and the high dielectric constant film and the low dielectric film are formed on these lower electrodes in the order. The low dielectric constant film in a region in which the large capacitor is to be formed is removed and the upper electrodes of the small and large capacitors are simultaneously formed on the low dielectric constant film in a region in which the small capacitor is to be formed and on the high dielectric constant film in the region in which the large capacitor is to be formed. Thus, the semiconductor device including the small and large capacitors having the simultaneously formed lower electrodes, the high dielectric constant film simultaneously formed as the inter-electrode dielectric layer, the low dielectric constant film formed in the inter-electrode layer of only the small capacitor and the upper electrodes formed simultaneously as the same conductive film.
It is preferable to form at least one active element and to form the lower electrodes of the small and large capacitors simultaneously with a formation of an electrode of the active element.
In detail, the active element is formed on the substrate, a metal film used to form the electrode of the active element is left on at least two portions of said substrate, the active element and the metal film are covered by an inter-layer film, openings are formed in the two regions of the inter-layer film to expose portions of the metal film, a second dielectric film having a high dielectric constant and a first dielectric film having a low dielectric constant are laminated, the first dielectric film is removed from one of the two regions, in which the large capacitor is to be formed, and the small capacitor and the large capacitors are formed in the region in which the low dielectric constant film exists and the large capacitor is formed in the region from which the low dielectric constant film is removed, by processing the conductive film.


REFERENCES:
patent: 4811076 (1989-03-01), Tigelaar et al.
patent: 4918454 (1990-04-01), Early et al.
patent: 5304506 (1994-04-01), Porter et al.
patent: 5736421 (1994-11-01), Shimomura et al.
patent: 4-229646 (1992-08-01), None
patent: 6-120425 (1994-04-01), None
patent: 7-221268 (1995-08-01), None
patent: 8-139273 (1996-05-01), None
patent: 8-340083 (1996-12-01), None
patent: 9-82896 (1997-03-01), None
patent: 9-102585 (1997-04-01), None
patent: 9-289287 (1997-11-01), None

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