Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-04
2001-07-24
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S591000, C438S762000, C438S954000
Reexamination Certificate
active
06265261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method in which the period of time for forming a nitride layer of a capacitor having an NO (nitride-oxide) dielectric layer is shortened.
2. Background of the Related Art
In general, as the integration of semiconductor memory devices (e.g., DRAMs) increases, the dimensions of the memory cells and the capacitors of the device decrease. Accordingly, as the capacitance of the capacitor of the memory cells is reduced, it becomes more difficult to achieve a capacitance sufficiently high enough to prevent product reliability problems in the semiconductor memory device.
In order to solve the aforementioned problem, researchers have concentrated on methods such as expanding the valid area of the capacitor, utilizing a dielectric layer having a high dielectric constant, or thinning the dielectric layer itself. In order to expand the valid area of the capacitor, an ONO (native oxide-nitride-top oxide) dielectric layer, which is a multiple insulating layer, has been utilized in constructing the semiconductor device in the deposition structure, instead of the planar structure.
However, there are some drawbacks to this method. If the thickness of the nitride layer is decreased in the process of forming the ONO dielectric layer of the capacitor, the internal oxidation pressure of the top oxide layer reduces product reliability. If the thickness of the oxide layer is decreased while forming the ONO dielectric layer of the capacitor, the leakage current increases. In this regard, there have been limitations in forming the ONO layer at a thickness of less than 50 Å.
In order to solve the limitations described above, an NO (nitride-oxide) layer has been substituted for the conventional ONO dielectric layer. In other words, NH
3
gas is used in low pressure chemical vapor deposition (LPCVD) equipment to nitride a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of the capacitor in the in-situ state into a Si
3
N
4
layer, which will help shorten the incubation time at the following step of forming a nitride layer. Then, the nitride layer is deposited on the Si
3
N
4
layer in the in-situ state to thereby complete the formation of a preferred nitride layer as a whole, and an oxide layer is further deposited onto the nitride layer to complete the formation of a dielectric layer having the NO structure of the dielectric layer.
However, as shown in
FIG. 1
, after the step of forming the pattern of polysilicon layers to be used as the lower electrode, the silicon substrate is transferred into a boat of the LPCVD equipment, and the boat is further loaded onto a tube as the temperature of the tube is increased to 650° C. from the standby temperature of 550° C. When the boat is completely loaded, the temperature of the tube is increased to 780° C. (T
1
) in preparation for nitriding the native oxide layer on the pattern of polysilicon layers to be used as the lower electrode. Ammonia gas is then allowed to flow into the tube for nitriding the native oxide layer on the polysilicon layer to be used as the lower electrode. Afterwards, the temperature T
1
of the tube is decreased to 670° C. (T
2
) for depositing the nitride layer in the in-situ state.
However, since T
1
is higher than T
2
, gaseous particles are easily activated in the tube at T
1
. A great deal of pumping time has been required for decreasing the pressure of the tube to the base vacuum level before commencing the nitriding of the native oxide. In addition, a predetermined period of time has been required for increasing the temperature of the tube to T
1
and for decreasing the temperature of the tube from T
1
to T
2
. Consequently, a great deal of time has been taken for completing the formation of the entire nitride layer which makes up the lower portion of the NO dielectric layer of the capacitor.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method of fabricating a semiconductor device which shortens the period of time required for forming an entire nitride layer of an NO dielectric layer without reducing the quality of the NO dielectric layer.
In order to accomplish the aforementioned object of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of: forming a pattern of polysilicon layers to be used as the lower electrode of a capacitor on the silicon substrate; forming an entire nitride layer by nitriding a native oxide layer on the pattern of polysilicon layers at a predetermined temperature in the LPCVD process and then depositing a nitride layer onto the nitrided native oxide layer in the in-situ state at the same temperature as the aforementioned predetermined temperature; depositing an oxide layer onto the entire nitride layer; and forming a pattern of upper electrodes on the oxide layer.
It is preferable that the native oxide layer be nitrided at a temperature of 670° C. Also, the pressure for nitriding the native oxide layer should be kept at more than 40 Pa. Therefore, according to the present invention, the native oxide layer on the pattern of polysilicon layers to be used as the lower electrode of the capacitor is nitrided in the LPCVD equipment at a constant temperature in the environment of ammonia gas, and the nitride layer is deposited onto the nitrided native oxide layer in the in-situ state, thereby shortening the period of time for forming the nitride layer of the NO dielectric layer.
REFERENCES:
patent: 5422291 (1995-06-01), Clementi et al.
patent: 5504021 (1996-04-01), Hong et al.
patent: 5629221 (1997-05-01), Chao et al.
patent: 5953608 (1999-09-01), Hirota
An Joong-il
Hyon Kyoung-Ho
Kim Ki-Young
Koo Byung-Su
Elms Richard
Jones Volentine, LLC
Lebentritt Michael S
Samsung Electronics Co,. Ltd.
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