Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-11-09
2002-01-29
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S203000, C365S207000
Reexamination Certificate
active
06343035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device internally provided with a data bus.
2. Description of the Background Art
In a semiconductor device, the simplest method of transferring data from one functional block to another is to use one internal data bus for one bit of data, and to set that one internal data bus to the logic high or “H” level, or to the logic low or “L” level.
Such an internal data bus is herein referred to as a single data bus.
FIG. 11
is a diagram relating to a description of a single data bus in a conventional semiconductor device.
In
FIG. 11
, semiconductor device
701
includes an internal circuit
702
which is a first functional block, and an output circuit
704
which is a second functional block for receiving data from internal circuit
702
via a single data bus and for outputting the data to an external data bus
708
.
Internal circuit
702
generates a data signal DATA internally and includes inverters
728
and
730
connected in series for amplifying data signal DATA and for outputting the amplified signal on the single data bus.
Output circuit
704
includes an inverter
748
for receiving and inverting a clock signal CLKO, a transmission gate
750
for taking in the data on the single bus according to clock signal CLKO and to an output from inverter
748
, inverters
752
and
754
forming a latch circuit for latching the data taken in by transmission gate
750
, an inverter
756
for receiving and inverting an output enable signal OE, and P-channel MOS transistors
758
,
760
and N-channel MOS transistors
762
,
764
connected in series between a power-supply node and a ground node.
P-channel MOS transistor
758
receives an output from inverter
756
at a gate. N-channel MOS transistor
764
receives output enable signal OE at a gate. Thus, P-channel MOS transistor
758
and N-channel MOS transistor
764
are activated when output enable signal OE is at the “H” level so that outputting of data becomes possible.
P-channel MOS transistor
760
and N-channel MOS transistor
762
receive an output from inverter
752
at the gates. The node connecting P-channel MOS transistor
760
and N-channel MOS transistor
762
forms an output node for output circuit
704
, and is connected to external data bus
708
. Other semiconductor devices
710
and
712
are connected to external data bus
708
.
Semiconductor devices
710
and
712
include output circuits similar to that in semiconductor device
701
, and the output nodes of these output circuits are connected to external data bus
708
.
Generally, when a plurality of semiconductor devices share one external data bus as in
FIG. 11
, an output circuit is driven during the period in which data is effective and outputs the data to the external data bus, while the external data bus is cut off from output circuit during the period in which data is ineffective. The output circuit may be cut off from the external data bus by setting output enable signal OE to the “L” level.
FIG. 12
is an operational waveform chart for semiconductor device
701
shown in
FIG. 11
when outputting data.
Referring to
FIG. 12
, let us consider the case in which internal circuit
702
outputs data signal DATA at time t
1
. The data signal transmitted via a single bus as far as the vicinity of output circuit
704
is referred to as DATAD. Due to propagation delay of data, at time t
1
, data signal DATAD has not yet been transmitted so that the data on the data bus is ineffective.
At time t
2
, data signal DATAD becomes effective. At time t
3
, clock signal CLKO and output enable signal OE, which serve as trigger signals to decide the timing at which data is output to the external data bus, are activated after data signal DATAD definitely attains the effective state, and thereafter, effective data is output on an external data bus EBUS.
If, for instance, clock signal CLKO and output enable signal OE are activated before time t
2
, ineffective data would be output on external data bus EBUS.
There also is, however, a potential problem, in avoiding outputting of ineffective data, that the timing for outputting data could be delayed if the timing at which clock signal CLKO and output enable signal OE are activated is held off too long after the time when data becomes definite at time t
2
.
This problem may be circumvented by the use of a complementary data bus.
FIG. 13
is a diagram related to a description of a complementary data bus.
As shown in
FIG. 13
, semiconductor device
801
includes an internal circuit
802
for internally generating and outputting complementary data signals DATA and ZDATA, a complementary data bus
806
for receiving outputs from internal circuit
802
, and an output circuit
804
for receiving data from the complementary data bus and for outputting the received data to the outside.
Internal circuit
802
includes inverters
828
and
830
connected in series for outputting data signal DATA to the complementary data bus
806
, and inverters
832
and
834
connected in series for receiving data signal ZDATA complementary to data signal DATA and for outputting the received data signal to complementary data bus
806
.
Complementary data bus
806
includes a data bus line
806
a
for transmitting a data signal DATAD corresponding to data signal DATA to output circuit
804
, and a data bus line
806
b
for transmitting a data signal ZDATAD corresponding to data signal ZDATA to output circuit
804
.
Output circuit
804
includes an inverter
852
for receiving and inverting data signal DATAD, and a P-channel MOS transistor
860
and an N-channel MOS transistor
862
connected in series between a power-supply node and a ground node. A gate of P-channel MOS transistor
860
receives an output from inverter
852
. A gate of N-channel MOS transistor
862
receives data signal ZDATAD. The node connecting P-channel MOS transistor
860
and N-channel MOS transistor
862
forms an output node for output circuit
804
, and is connected to external data bus
808
.
Other semiconductor devices
810
and
812
are connected to external data bus
808
. Semiconductor devices
810
and
812
include output circuits similar to that in semiconductor device
804
, and the output nodes of these output circuits are connected to external data bus
808
.
FIG. 14
is an operational waveform chart related to a description of an operation of the complementary bus shown in FIG.
13
.
Referring to
FIGS. 13 and 14
, data signals DATA and ZDATA are both at the “L” level before time t
1
. This state is the standby state of the complementary bus.
At time t
1
, one of data signals DATA and ZDATA attains the “H” level and the effective data is output.
At time t
2
, one of data signals DATAD and ZDATAD after the delay time caused by complementary data bus
806
attains the “H” level, and the effective data is propagated to output circuit
804
. Accordingly, at time t
3
, one of P-channel MOS transistor
860
and N-channel MOS transistor
862
is rendered conductive, and the effective data is output to external data bus
808
.
Since the standby state of the complementary bus is defined by the condition of both P-channel MOS transistor
860
and N-channel MOS transistor
862
being non-conductive, the transition of data from its ineffective state to the effective state triggers the outputting of the data to the external data bus. Therefore, when compared with the case of
FIG. 12
, the delay time between time t
2
and time t
3
is substantially eliminated and the period for which data is effective is fully utilized in the case of FIG.
14
.
Next, let us consider a case in which the single data bus shown in
FIG. 11
has a very heavy load capacitance.
FIG. 15
is an operational waveform chart of a case in which a single data bus has a heavy load capacitance.
As shown in
FIGS. 11 and 15
, the data of data signal DATA becomes effective at time t
1
. Since, however, the load capacitance of the single data bus is great, a very lon
Hamamoto Takeshi
Kubo Takashi
Setogawa Jun
Dinh Son T.
McDermott & Will & Emery
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