Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-05-18
2001-02-06
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S194000, C365S201000
Reexamination Certificate
active
06185141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device which allows efficient evaluation of fast operation.
2. Description of the Background Art
In recent years, it has been increasingly demanded to increase operation speeds of semiconductor devices. For satisfying such demand, more severe timing accuracy have been required in a so-called memory tester, which is a checking device for executing operation check in a check step.
Particularly, some semiconductor memory circuits of a clock synchronous type require an external clock frequency of 100 MHz or more (cycle time of 10 ns or less) so that such a problem is now arising that a conventional memory tester cannot sufficiently perform the operation check. A memory tester, which can operate fast and will also be referred to as a “fast tester”, is more expensive than a conventional tester which will be referred to as a “slow tester”. Therefore, it is now one of important matters to suppress rise in test cost which may be caused by increase in operation speed of the semiconductor device.
A problem of the prior art will be described below taking as an example an evaluation test of a minimum write recovery time in a Synchronous Dynamic Random Access Memory (SDRAM).
A write recovery time tWR is defined as a period from input of a write command to instruction of a precharge operation. The normal write operation must be ensured when the write command is issued or the precharge operation is instructed so that tWR is equal to or longer than the minimum write recovery time.
Accordingly, the check step is performed in such a manner that the memory tester externally applies to the SDRAM signals for enabling production of the write command within the SDRAM and execution the precharge operation, and commands are internally produced in accordance with these signals to check whether the normal write operation can be executed or not. For evaluating the minimum write recovery time in the fast operation, therefore, the memory tester must apply the test signal which can continuously cause the above operations for a very short period.
FIG. 10
is a circuit diagram showing a structure of a precharge control circuit
500
in the prior art.
Referring to
FIG. 10
, precharge control circuit
500
controls activation (H-level) and inactivation (L-level) of a precharge control signal Prec for executing precharging.
In the normal operation, a combination of the signal levels of externally applied control signals determines whether the precharge operation is to be performed or not. In an operation of measuring a minimum write recovery time, precharge signal Prec can be activated in accordance with the signal level of a test signal TWRTST.
Referring to
FIG. 10
, precharge control circuit
500
includes a logic gate
510
receiving a control signal CS, which is an inverted signal of a chip select signal /CS, a control signal RAS which is an inverted signal of a row address strobe signal /RAS, and a control signal WE which is an inverted signal of a write enable signal /WE, and issuing a result of an NAND operation among these signals, an inverter
515
inverting the output of logic gate
510
, and a logic circuit
520
issuing a result of an OR operation between the output of inverter
515
and test signal TWRTST.
Precharge control circuit
500
further includes an inverter
525
inverting control signal WE, a logic gate
530
which issues a result of an AND operation between test signal TWRTST and the output of inverter
525
, and a logic circuit
540
issuing a result of an AND operation between the outputs of logic circuit
520
and logic gate
530
. Logic circuit
540
issues precharge control signal Prec.
In the synchronous semiconductor memory device, various commands are produced in accordance with combinations of the signal levels of various control signals at the activation edge of an external clock signal.
In the normal operation, test signal TWRTST is inactive and at L-level. Therefore, precharge signal Prec is activated (H-level) when control signal /CS is at L-level (CS is at H-level), signal /RAS is at L-level (signal RAS is at H-level), signal /CAS is at H-level and signal /WE is at L-level (WE is at H-level).
FIG. 11
is a timing chart showing a method of measuring a write recovery time in a normal operation mode of precharge control circuit
500
.
Referring to
FIG. 11
, an activate command is produced to activate a word line WL at time t0 prior to production of a write command.
After production of the activate command, a write command is produced at the activation edge of the external clock signal at time t1 (/CS=L-level, /RAS=H-level, /CAS=L-level and /WE=L-level). In response to this, an internal write control signal int.WRT is activated to attain at H-level in the SDRAM at time t2.
At time t3, i.e., at the next activation edge of the external clock signal, a precharge command is produced (/CS and /RAS=L-level, /CAS =H-level, and /WE=L-level). In response to this, precharge control signal Prec is activated, and word line WL is inactivated at time t4. In the above operation, data writing in the SDRAM is allowed for a period from time t2 to time t4.
A write recovery time to be ensured according to specifications is defined by a period tWR between production of the write command and production of the precharge command. In the check operation, therefore, it is necessary to check whether the actual write operation is executed correctly or not, by varying write recovery time tWR by the memory tester.
In the normal operation mode, and therefore when test signal TWRTST is inactive (L-level), precharge control signal Prec can be controlled only by the combination of the signal levels of various control signals at the time of activation of external clock signal EXT.CLK. Therefore, the executable fastest test depends on the operation frequency of the memory tester. Therefore, if the test requiring severe timing control were to be executed in the above situation, a fast memory tester would be required, resulting in rise in cost.
In the test mode (which may also be referred simply to as a “test mode” hereinafter) for measuring the minimum write recovery time, i.e., in the case where test signal TWRTST is active (H-level), the output of logic circuit
520
in the circuit shown in
FIG. 10
is always at H-level so that precharge control signal Prec can be set by the signal level of control signal WE.
FIG. 12
is a timing chart showing a method of evaluating the write recovery time in the test mode by the precharge control circuit in the prior art.
Referring to
FIG. 12
, the activate command is issued to activate word line WL at time t0, similarly to the case in FIG.
11
.
At time t1, i.e., at the rising edge of external clock signal EXT.CLK, the signal levels of various control signals are set to produce the write command. The signal level of write enable signal /WE is kept at L-level for a period from a time earlier by a predetermined setup time tIS than time t1 to a time (time t3) later by a predetermined hold time tIH than time t1. In accordance with this, internal write control signal int.WRT is activated (H-level) within the SDRAM at time t2.
Together with the production of this write command, test signal is activated (not shown), whereby precharge control circuit
500
activates precharge control signal Prec to attain H-level in accordance with the change of write enable signal /WE to H-level at time t3. In response to this, word line WL is inactivated at time t4. In the above operation, the data writing within the SDRAM is actually allowed for a period from time t2 to time t4.
In this case, therefore, the precharge operation can be automatically executed in accordance with change in signal level of write enable signal /WE to the H-level after instruction by the write command. Therefore, the precharge operation can be executed subsequently to the write command in accordance with timing shorter than the p
Hoshita Tetsushi
Ikeda Yuto
Dinh Son T.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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