Semiconductor device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189170

Reexamination Certificate

active

07940576

ABSTRACT:
There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value.

REFERENCES:
patent: 5771199 (1998-06-01), Lee
patent: 6310816 (2001-10-01), Manning
patent: 6414868 (2002-07-01), Wong et al.
patent: 2004/0032776 (2004-02-01), Kim et al.
patent: 2005/0276146 (2005-12-01), Ha et al.
patent: 2006/0018168 (2006-01-01), Kim
patent: 2008/0201548 (2008-08-01), Przybylski et al.
patent: 2003-143240 (2003-05-01), None
patent: 2005-056529 (2005-03-01), None
patent: 2005-317124 (2005-11-01), None
patent: 100550643 (2006-02-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Feb. 11, 2011.

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