4. Static information storage and retrieval
  5. Read/write circuit
  6. Having particular data buffer or latch

Bo-Kyeom Kim

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Digital delay locked loop circuit using mode register set

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate

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Semiconductor device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Semiconductor memory device and operating method thereof

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2236333

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