Semiconductor device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S733000, C714S739000

Reexamination Certificate

active

08037384

ABSTRACT:
A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.

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patent: 7058869 (2006-06-01), Abdel-Hafez et al.
patent: 7234092 (2007-06-01), Cooke
patent: 7581149 (2009-08-01), Sugawara
patent: 7735049 (2010-06-01), Wang et al.
patent: 2009/0292926 (2009-11-01), Daskalopoulos et al.
patent: 10-170609 (1998-06-01), None
patent: 2001-174515 (2001-06-01), None

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