Semiconductor circuit apparatus and scan test method for...

Details Semiconductor circuit apparatus and scan test method for... Semiconductor circuit apparatus and scan test method for...

2008-05-27

2008-05-27

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S718000

Reexamination Certificate

active

07380183

ABSTRACT:
A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between flip-flops included in the scan chain, a first bypass path bypassing the first macro cell, a first selection circuit selecting the first macro cell or the first bypass path, a second macro cell placed in a path between flip-flops included in the scan chain, a second bypass path bypassing the second macro cell, and a second selection circuit selecting the second macro cell or the second bypass path. The first selection circuit and the second selection circuit operate individually.

REFERENCES:
patent: 5477545 (1995-12-01), Huang
patent: 6327683 (2001-12-01), MacCormack
patent: 2004/0128604 (2004-07-01), Guettaf
patent: 11-083958 (1999-03-01), None
patent: 2001-042008 (2001-02-01), None
patent: 2003-0027989 (2003-04-01), None
Kwon et al., FakeFault: A Silicon Debug Software Tool for Microprocessor Embedded Memory Arrays, 1998, IEEE, pp. 727-732.

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