4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Hiroki Machimura

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Cache memory and control method thereof

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selectively debugging processor cores through instruction codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Semiconductor circuit apparatus and scan test method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Semiconductor circuit apparatus and scan test method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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