Semiconductor chip package using improved tape mounting

Details Semiconductor chip package using improved tape mounting Semiconductor chip package using improved tape mounting

1996-07-22

1997-11-04

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

257676, 257691, 257783, H01L 23495, H01L 2352

Patent

active

056843283

ABSTRACT:
An LOC type semiconductor package and a fabricating method thereof comprises first and second through holes formed at inner leads and bus bars of the LOC-type lead frame, and third through holes formed at the tape which is bonded with the lower side of the inner leads and the bus bars, by pins at a tape cutter. Thus, air existing at both tape during the bonding process effectively flows out so as to prevent the trapping of air bubbles. Accordingly, during the wire bonding process, wire shorting and damage to the package body can be prevented. Since EMC is deposited into the first and the second through holes and supports the inner leads and the bus bars during the molding of the semiconductor package, the reliability of the semiconductor package can be improved.

REFERENCES:
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William C Ward, Volumn Production of Unique Plastic Surface-Mount Modules for the IBM 80-NS 1-MBIT DRAM Chip by area Wire Bond Techniques, IBM General Technology Division, Essax Junction, Vermont, pp. 552-557.

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